VHDL Comparator 4-bit

[tonionio]

Dear all ,

I am trying to build a comparator in VHDL for a 5-port router north port ,south , east ,west and local port to processing unit

I will have an input of 4 bits and these 4 bits will be compared with some x,y coordinates stored for each router's comparator. So lets say that the coordinates are x=1 and y=2 .

The coordinates show the position of a router in a mesh network. So if we have a 4x4 mesh network router 1 2 (xy) will be the second line and thrid row router.

So I want to compare the first 2 input bits (00 , 01 , 10 ,11) out of the 4 with the x coordinate of the router which we said is '1' decimal.
So again lets say that the first 2 bits are (11 binary =3 decimal)

I need to compare: if 2_first_input_bits > x where x is 1 then
out <= '000' where 000 indicates that we need use the east port of the router
elsif 2_first_input_bits < x where x is 1 then
out <= '001' where 001 indicates the west port
elsif 2_first_input_bits = x where x is 1 and 2_second_input_bits > y then
out <= '010' where 010 indicates the north port
elsif 2_first_input_bits = x where x is 1 and and 2_second_input_bits < y then
out <= '011' where 011 indicates the south port
else out <= '100' where 100 indicates the local port

end if ;


So my problem is that I cannot understand how to convert the binary to decimal and how to split the 4 input bits to two segments and use the for each coordinate.

 

[TrickyDicky]

try using the numeric_std package, then you can easily do

if two_bits > 1 and y > 1 then

etc.

 

[tonionio]

try using the numeric_std package, then you can easily do

if two_bits > 1 and y > 1 then

etc.

Cant really understand what you mean!

How can I split the 4 input bits into two segments so I can use the first two for comparison with x coordinate and the next two for y coordinate.

I do not know what the numeric_std package will do!Will it convert the binary input bits to decimal?

 

[TrickyDicky]

On real hardware there is no such thing as decimal. All numbers are binary. In VHDL you can compare arrays to decimal values just so its easy to read.

You can split up any array by indexing the bits:

if din(1 downto 0) > 1 then
..
elsif din(3 downto 2) > 1 then

etc.

You need to use the numeric_std package to convert the input to unsigned/signed types, assuming they are not that type already (they will probably be std_logic_vectors).

I highly suggest reading a VHDL tutorial as this is pretty basic stuff.

 

[tonionio]

Could you please suggest a good tutorial to begin with?
I am trying to find something online but I am not sure what will do the job.

thank you for your time .

 

[tonionio]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all

entity xy_rout is

Port ( x : in STD_LOGIC_vector ( 3 downto 0);
Hx: in std_logic_vector ( 1 downto 0);
Hy :in std_logic_vector ( 1 downto 0);
y : out STD_LOGIC_vector ( 2 downto 0);
);
end xy_rout;

architecture Behv of xy_rout is

begin
process(x,Hx,Hy,y)

if (x(1 downto 0)) > Hx then

y<= "000"; --where 000 signifies the use of the east output
elsif (x(1 downto 0)) < Hx then
y<= "001"; -- usage of the west port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) > Hy then
y<= "010"; -- usage of the north port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) < Hy then
y<= "011"; -- usage of the south port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) = Hy then
y<= "100"; -- usage of the local port

end Behavioral;




ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 5: Syntax error near "entity".
ERROR:HDLCompiler:374 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 14: Entity <xy_rout> is not yet compiled.
ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 19: Syntax error near "if".


I am getting these mistakes but I cannot understand whats wrong

 

[VishwanathAmbli]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all

entity xy_rout is

Port ( x : in STD_LOGIC_vector ( 3 downto 0);
Hx: in std_logic_vector ( 1 downto 0);
Hy :in std_logic_vector ( 1 downto 0);
y : out STD_LOGIC_vector ( 2 downto 0);
);
end xy_rout;

architecture Behv of xy_rout is

begin
process(x,Hx,Hy,y)

if (x(1 downto 0)) > Hx then

y<= "000"; --where 000 signifies the use of the east output
elsif (x(1 downto 0)) < Hx then
y<= "001"; -- usage of the west port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) > Hy then
y<= "010"; -- usage of the north port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) < Hy then
y<= "011"; -- usage of the south port
elsif (x(1 downto 0)) = Hx and (x(3 downto 2) = Hy then
y<= "100"; -- usage of the local port

end Behavioral;




ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 5: Syntax error near "entity".
ERROR:HDLCompiler:374 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 14: Entity <xy_rout> is not yet compiled.
ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 19: Syntax error near "if".


I am getting these mistakes but I cannot understand whats wrong

you have written Behv at the inception of architecture but at the end you have used Behavioral so just check with this:

 

[tonionio]

ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 5: Syntax error near "entity".
ERROR:HDLCompiler:374 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 14: Entity <xy_rout> is not yet compiled.
ERROR:HDLCompiler:806 - "C:\Users\tonionio\Desktop\XY\xy_routing\xy_rout.vhd" Line 19: Syntax error near "if".

I am still getting these errors

 

[VishwanathAmbli]

use begin after the the process and end process; where the process block ends... try this:

 

[TrickyDicky]

Lots of very basic problems:
1. Remove the ; from the y port
2. "end process" needed to end the process
3. Several brackets missing in the process
4. No type conversions to make the bit extractions signed or unsigned type.

 

[tonionio]

Everything ok finally!I got it to work and I ve testbench it as well together with some other parts of my project!

I am now into implementing an arbiter for the project! I have found this code : https://www.asic-world.com/examples/vhdl/arbiter.html

Could someone please explain the need of the internal registers and in general the main code together with the state machine and other parts!

 

[tonionio]

any one please ?

 

[tablekursi]

how to write testbench for it

- - - Updated - - -

there is an error in process statement Object y of mode OUT can not be read.

 

[tablekursi]

dear tonionio,
I constructed the fifo using logicore now I want to know how it is instantiated.