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Need a verilog code for the follwoing..please help

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vaasu01

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Hi every one..

Please give the verilog code for following..

A Updown counter of 4 bit..if preset is high..it should count from 5 to 15..please help me..this was asked in an interview..
 

vaasu01 said:
Hi every one..

Please give the verilog code for following..

A Updown counter of 4 bit..if preset is high..it should count from 5 to 15..please help me..this was asked in an interview..
Click to expand...



hello,
Here is the code for ur counter specification, hope it helps u.
 

Attachments

  • updown4b.txt
    516 bytes · Views: 48

I m Sorry sir..Could you please give me a verilog code instead of VHDL.. and i want to repeat my question once again..


A 4 bit up down counter where as if preset is 1 it should count in 5 to 15( both up n down conditions apply) n if preset is 0., it should work like normal up down counter...



Thanking you
 

delete/comment this part of the code in program
and it works as a normal counter wen preset is 0 and in a way u mentioned wen preset is 1.

if(count="0101") then
count<="1111";
end if;
 

Sorry,,sir i did nt get u..u didnt consider updown ,,so what if preset is 1 and updown=0( i.e., down count which doesnot cover 0,1,2,3,4)
 

i hope this code does the work, if not plz define ur problem statement again.
giving information on wat inputs u want and how u want the counter to behave wen the present is on.( in both modes up and down).
 

Attachments

  • updown.txt
    676 bytes · Views: 46

sorry sir,,i m beginner..i m more familiar with verilog code,not with VHDL..

Thanking you..
 

could u please send me .v or .vhd file..in above file u gave got some errors..

thanking u
 

this is the main vhdl code:
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity updown4b is
port(count: inout std_logic_vector(3 downto 0):="1111";updown: in std_logic ;clk: in std_logic;preset:in std_logic);
end updown4b;

architecture Behavioral of updown4b is

begin
process(clk)
begin

if(clk'event and clk='1') then
   if(updown='0') then
       count<=count-1;
		 --if(count="0101") then
		    --count<="1111";
		 --end if;	 
	end if;
	if(updown='1') then 
	    --count<="0101";
		 count<=count+1;
       if(count="1111") then
       count<="0000";
       end if;
	end if;
	if(preset='1') then
	    count<="0101";
		 count<=count+1;
		 if(count="1111") then
		   count<="0101";
		 end if;	
   end if;		 
end if;	
end process;	
end Behavioral;
and test bench for the above prog is :
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_updn_vhd IS
END tb_updn_vhd;

ARCHITECTURE behavior OF tb_updn_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT updown4b
	PORT(
		updown : IN std_logic;
		clk : IN std_logic;
		preset : IN std_logic;       
		count : INOUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL updown :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL preset :  std_logic := '0';

	--BiDirs
	SIGNAL count :  std_logic_vector(3 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: updown4b PORT MAP(
		count => count,
		updown => updown,
		clk => clk,
		preset => preset
	);

	tb : PROCESS
	BEGIN
	
	clk<='0';
	wait for 10 ns;
	clk<='1';
	updown<='0';
	preset<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	updown<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	preset<='0';
	updown<='0';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	updown<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
	

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;

i hope dis helps u:
 

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