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I am using Cadence Virtuoso 6.1.3. i ran a single point monte carlo transient analysis for my design. I used the ocean script below to write the results into a text file
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out = outfile("/home/analog/MyOutputFiles/my_ckt_output.out"...
Hi,
I did a transient run in monte carlo analysis in Virtuoso ADEXL. After the run i used an ocean script to save the output voltage at specific time instances. The code I used is given below
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out =...
This a BGR circuit isnt..
The function of the opamp is to make the volates at its input equal.
So say u r designing it for a voltage of 1.262V
The ratio of areas of Q1 to Q2 is say n
So we can say
Vbe1 = Vbe2 + I*R1
I = (Vbe1-Vbe2)/R1
I is the current
i.e I = VT*ln(n)/R1
VT is the thermal...
U can use this..
ABA
BAB
But always try to make the fingers in multiple of 4. It will make ur design clean and will b more easy to connect and implement the common centroid
OCEAN simulation errors
In order to calculate the node voltages u need a ground reference. Like for example u have to capacitors connected in series then the node between them is floating in DC analysis. But to find the initial condition the tool must have a voltage there. So it assumes the...
Sorry my mistake...I didnt notice the value of m
In your design you can increase the gain by increasing the gain of the second stage.
Otherwise try using other configurations of opamp which gives higher gain
In the picture of the diff amp u send why all the transistors are of the same size. It wont come like that in the design. Recheck ur design.
Run the simulation for a long frequency range.
Add a miller compensation capacitor.
It will be also really good if u give the inputs to the diffamp...
Can u change the x axis to logarithamic. I cant make out the frequency response from this picture...
Can u also show the circuit u designed. The mirror wont give the same current if the voltage available in the output section of the mirror is not enough to keep it in saturation
AMS 0.35um pads
hi...
i am doing a design which has both digital and analog parts. after completing the layout and verification i added pads to the core module.
I used digital pads from IOLIB_4M and analog pads from IOLIB_ANA_4M. Inside the pads i used there are global nets such as vdd3r...
Floating psub
Your substrate is always prone to noise. Its also necessary to bias the substrate to avoid latchup problems...
So it is essential to connect the substrate to the lowest potential...
Plus the threshold voltages of MOS depends on the biassing of the substrate... So if you dont...
One of the best topic u can select is design of ADC or DAC,like a sigma delta ADC.
It will have both analog and digital protions and it will help a lot in familirizing the concepts of analog, digital and mixed designs....
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