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Re: what this code mean
It looks like a shifter i think.
any way i am explaining u the code.
always @ poedge of clock-------- it is clear that the following work will be done when the +ve edge of clk comes.
secondly the if(load) condition means that if load =1 then the following conditions...
l2 ethernet switch design fpga
go to xilinx website www.xilinx.xom
There is a section of application notes inwhich u can find design notes on ethernet switch.
Re: GAL and FPGA
GAL is pretty outdated.
GAL and FPGA are two different things. About as much difference between a bycicle and a Ferrary. PAL is a SPLD (simple programmable logic device). An FPGA is like a super-boosted PLD.
Re: dsp processor?
well the TI dsp's are the best i think at the moment.
U can use their development kit TMS3206007 or any ither.
And there is a very good by Rulph Chassassing DSP Applications using the TMS3206xxx DSK
Using a TI's DSK and this book u can make a great progress in DSP processors.
Re: FPGA selection
The best way to choose is to make a list of ur requirements and then go on a specific vendor's website and then select any one.
FPGAs come in many variety so it is important for u to identify ur requirements.
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