What does this code mean ?

[v9260019]

module CREG (clk, data_in , load, up, clr, data_out );
parameter size=8;
input [size-1:0] data_in;
wire [size-1:0] data_in;
input clk,load, up, clr;
output [size-1:0] data_out;
reg [size-1:0] data_out;
always @ (posedge clk)
if (load) data_out<=data_in;
else if (up) data_out<=data_out+1;
else if (clr) data_out<=0;
endmodule

(hello all
anybody can tell me what the following code mean??????)

always @ (posedge clk)
if (load) data_out<=data_in;
else if (up) data_out<=data_out+1;
else if (clr) data_out<=0;

 

[pisoiu]

what this code mean

Looks like a presetable synchronous 8 bit counter. Actions (preset - controlled by (load), count - (up), clear - (clr)) takes place at 0 to 1 transition of clk.

/pisoiu

 

[umairned]

Re: what this code mean

It looks like a shifter i think.
any way i am explaining u the code.

always @ poedge of clock-------- it is clear that the following work will be done when the +ve edge of clk comes.

secondly the if(load) condition means that if load =1 then the following conditions will execute.

now this 'if' is nested as per ur design.

the rest is simple data_out<=data-in means that on this cond data at the input comes at the output

 

[visualart]

what this code mean

It is a INCrease counter from data-in.
If the load is the true, the jumping-off point will be loaded by the datain.

 

[echo47]

Re: what this code mean

It's a counter, like pisoiu said.

I think it's difficult to read that way, so I reformatted it:

module CREG (clk, data_in, load, up, clr, data_out);
  parameter             size = 8;
  input                 clk, load, up, clr;
  input      [size-1:0] data_in;
  output reg [size-1:0] data_out;

  always @ (posedge clk)
    if (load)
      data_out <= data_in;
    else if (up)
      data_out <= data_out + 1;
    else if (clr)
      data_out <= 0;
endmodule

I prefer putting all those if/else statements into one line:

always @ (posedge clk)
  data_out <= load ? data_in : up ? data_out + 1 : clr ? 0 : data_out;

 

[power-twq]

Re: what this code mean

always @ (posedge clk)
if (load) data_out<=data_in; // load data_in into counter;
else if (up) data_out<=data_out+1; // counter up by one per each clock edge
if up is active
else if (clr) data_out<=0; // clear counter


best regards

module CREG (clk, data_in , load, up, clr, data_out );
parameter size=8;
input [size-1:0] data_in;
wire [size-1:0] data_in;
input clk,load, up, clr;
output [size-1:0] data_out;
reg [size-1:0] data_out;
always @ (posedge clk)
if (load) data_out<=data_in;
else if (up) data_out<=data_out+1;
else if (clr) data_out<=0;
endmodule

(hello all
anybody can tell me what the following code mean??????)

always @ (posedge clk)
if (load) data_out<=data_in;
else if (up) data_out<=data_out+1;
else if (clr) data_out<=0;

 

[nand_gates]

Re: what this code mean

In plain words this code is for paramiterable 8 bit Loadable synchronous up counter.
Using Load the counter gets loaded with data_in.
Using clear you can clear the counter to zero.
Using Up up counting is enabled.

Here Load has highest priority over up and clr inputs.
Up control has next highest priority over clr. This means
if Load is asserted up and clr are have no effect on output.
And if up and clr are asserted with load deasserted clr has no
effect the counter will continue to count up.

Last point to be noted is all three contols are synchronous!