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Recent content by tavidu

  1. T

    Primetime: disabling timing of high fanout pins

    set the output pins "ideal network"
  2. T

    how to implement DFT for DDR2

    ddr2 bist there are DDR2 controller in the chip which run at about 333MHz. Anyone do DFT for such high speed interface?
  3. T

    Wire area difference when using DC and RC for the same design

    when I use DC and RC(RTL compiler) for a same design, the gate count result is no much different, but wire area differ too much. Now I'm evaulate these two tools, and wire area is the one that I need to concern? Less wire area, more routable in layout period?
  4. T

    how is the inernal clocks of a chip generated?

    if the freq is not high, you can feed clock into your chip by external if the freq is high, you can your pll, for example, DDR,DDR2
  5. T

    critical path problem

    1.please synth your code first. and check your timing report.
  6. T

    What to work on first in crosstalk analysis?

    Re: Crosstalk analysis you can check it using primeime first
  7. T

    about FIFO,uses LFSR/Gray for read/write pointers

    grey code is enough for fifo design. note: you must resigter the grey encode pointer
  8. T

    evalute RC(CADENCE) and DC(SYNOPSYS)

    rc cadence Hi, I'm evaluting RC and DC. Anyone used these two synthesis tools? Which one is better for timing, area, power?
  9. T

    trace delay of PCB vary much in different PVT case?

    trace delay Hi, As we know, delay of gate in chip is different in different PVT, or in worst case and in best case. But in PCB, trace delay vary much in different case? For example, 5 inch length 's delay is 5*160 = 0.8ns accroding to 160ps/inch. 0.8ns is in which PVT case?
  10. T

    Question about trace delay on PCB

    Hi, As we know, delay of gate in chip is different in different PVT, or in worst case and in best case. But in PCB, trace delay vary much in different case? For example, 5 inch length 's delay is 5*160 = 0.8ns accroding to 160ps/inch. 0.8ns is in which PVT case?
  11. T

    how to find cells whose design name is "*AAA*"

    these cells are all in one level under current design. so dont need -hier. The "Error" come out because DC doesn't support "@ref_name==*AAA*"
  12. T

    how to find cells whose design name is "*AAA*"

    get_cells @ref_name hi, in my designs, there are designs named "XAAAX", "YAAAY", "ZAAAZ"..... I want to find all cell name whose design name is "*AAA*". get_cells * "@ref_name==*AAA*", but there are Error message .
  13. T

    POWER/GOURND PAD number selection

    Nobody can give me any suggestion? I just want assign POWER/GROUD PAD number for my chip. How many P/G group for core logic about 3,000,000 gate ccount and 4 Mbit SRAM? Assume for .13 um
  14. T

    POWER/GOURND PAD number selection

    how many sso(4mA driving) pads can 1 P/G support how many sso(8mA driving) pads can 1 P/G support how many sso(12mA driving) pads can 1 P/G support process: .13 generic TSMC process
  15. T

    how to use "compile" when have same design

    how to use "compile" when a design under a module is instaniated twice? For example: module TOP() D_SUB U_0(); D_SUB U_1(); endmodule when I compile TOP, DC Error infromation comes out. I don't want use "uniquify" to cheange D_SUB into 2 different design name. Thanks
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