Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how is the inernal clocks of a chip generated?

Status
Not open for further replies.

samuel

Full Member level 3
Joined
Nov 15, 2004
Messages
171
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Location
world
Activity points
1,143
by what means, i can implement this function.thankyouverymuch.
 

Typically you use a external clock and a PLL internally to synthesise the frequency that you want

then use divider or clock gaters to feed the clock to modules
 

U can use digital frequency synthesizer.
 

Hi,

i under stood u r problem that u want to design the circut which will generate internal clock.
u can done it by somany ways.
1. u can use the Pll to get the generated clock from the external clock.
2. u can use the counter which will give u the requred clock from higher frequency clock.

Regards,
Ramesh.S
 

internal oscillator can b created by using ring oscillator, but it is not really reliable.

it has a large variation across voltage and temperature variation..

so normally this internal oscillator is used for block that don't required fast frequency..

tht's my opinion..

sp
 

if the freq is not high, you can feed clock into your chip by external
if the freq is high, you can your pll, for example, DDR,DDR2
 

but when you use the external clock, you need the input buffer to improve the signal shape
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top