how to implement DFT for DDR2

[tavidu]

ddr2 bist

there are DDR2 controller in the chip which run at about 333MHz.

Anyone do DFT for such high speed interface?

 

[hawk_chenbo]

ddr2 ate

The ATE clock freqency is low, typically 10M. So you can meet setup time, you only need to consider hold time.

 

[chandhramohan]

dft for ddr2

Hi,

Yo can do DFT for the DDR2 / HSS / SERDES . But some special care needs to be taken . As for as JTAG is concerned you need to consider the TX & RX lines as clock and add appropraite Boundary scan cell for those pins . Special pads needs to be added which can support that frequency .

Mostly your DDR macro will be DFT inserted one . Refer to the data sheet for the TEst signals & scan chain ports etc

Hope you get some idea .

Regards
Chandhramohan

 

[dr_dft]

ddr2 high speed +ate

Testing DDR/DDR2 is a challange on most testers, since traditional testers are cycle based, and cannot deal with source synchronous interfaces too well.
There is an added complexity to these devices, the data strobe signal which acts as a 'source synchronous clock' for the data, is actually bidirectional.
There are several solutions to this problem, ranging from using a tester that can deal with source synchronous devices (may be expensive) to adding for BIST circuitry to test the interface.
You may be able to get better answers on **broken link removed**.