how to use "compile" when have same design

[tavidu]

how to use "compile" when a design under a module is instaniated twice?

For example:
module TOP()

D_SUB U_0();
D_SUB U_1();

endmodule

when I compile TOP, DC Error infromation comes out.
I don't want use "uniquify" to cheange D_SUB into 2 different design name.
Thanks

 

[Thomson]

Impossbile Consquence!

However try the following two steps instead of one:
<1> read -format verilog "source_name"
<2> elaborate module_name


vs.

read_verilog source_name!


Maybe helpful!


Thomson

 

[joe2moon]

In fact, you can achieve by the following steps:
===============================
step 1) compile/synthesize the design/module D_SUB first, and save the netlist to D_SUB_mapped.v

step 2) read in the TOP design which using D_SUB_mapped.v instead of D_SUB_rtl.v

step 3) compile TOP with don't touch on the instance U_0 and U_1.
---------------------------------------------------------------------------------------------

 

[yeewang]

current_design D_SUB
compile
set_dont_touch .....
current_design TOP
compile ....

sth. like that.

 

[Atre]

how to use "compile" when a design under a module is instaniated twice?

For example:
module TOP()

D_SUB U_0();
D_SUB U_1();

endmodule

when I compile TOP, DC Error infromation comes out.
I don't want use "uniquify" to cheange D_SUB into 2 different design name.
Thanks

I think your problem can be solved if you place DC in simple mode, where you can synthesize non-uniquified designs.

Hope this helps! :wink: