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Recent content by strennor

  1. S

    replica-feedback biasing for differential delay element

    1, How about the amplifier offset? How about the amplifier PSRR? I see the amplifier tail current depends on supply voltage. Have you tried use an ideal amp in the replica? or an amp with very good psrr? Could the jitter be better? 3, there are many types of delay stages, but it has very large...
  2. S

    Is noise analysis necessary for all analog IC designs?

    noise is quite critical, it depends on the application of your circuits, depends on what you are doing power relates with voltage through current offset can be reduced by larger transistor size, flicker noise is smaller for larger transistor size. noise is not important for some cases, maybe...
  3. S

    Process transconductance parameters kn,kp for AMI 0.6u

    do you have the pdk? calculate them from the model file. or, setup some simple circuits, simulate them
  4. S

    replica-feedback biasing for differential delay element

    1, i think the replica amplifier should be fast enough, the high frequency psrr should be good enough. is your amplifier an ideal one? 2, i read a document. the transistor ratio, between replica and delay cell, is 1:1 for loads, but 0.5:1 for the tail current source. What's your idea? 3, i...
  5. S

    Why vil and vih has to be calculated through dc sweep ??

    First of all, we talk about Vil/Vih or Vol/Voh only for Logic circuits. DC sweep sometimes suffers convergence problem. So we can try tran. When do tran sim, make sure the rising/falling time is long enough so that the results are close enough to DC results. To onlymusic16: plot your Vo vs...
  6. S

    how to realize a 150db open loop gain OP in CMOS process

    Omm... Are you designing TI's DRV603?
  7. S

    replica-feedback biasing for differential delay element

    Is it a symmetrical load delay stage? a few thoughts: 1, How about the PSRR of your amplifier? 2, the upper two PMOSs, the size is not identical, are you intend to do that? BTW what's the transistor ratio between this replica and the delay stages
  8. S

    bias circuit and differential buffer stage design

    1, You are right, the output is not rail-to-rail. It doesn't matter. 2, use a diff to single stage after it. take a look at another paper of the same author
  9. S

    How to start designing a PLL ?

    PLL Design I don't understand your question vey well. What are you going to have? You want exactly the same frequency and phase as the stable source? Why not use the frequency reference? What you need is only a buffer.
  10. S

    5V supply - low gain audio amplifier IC out there?

    Can you use resistor feedback to set the overall gain?
  11. S

    3 order delta sigma modulator in Matlab and Verilog

    Hi All, It has been a long time I read articals, download files, learn your experience here. Now it is time to share something. I just learned some delta-sigma modulator and did a simple Simulink model in Matlab with 32-bit realization, then a Verilog code 24bit realization with testbench. A...
  12. S

    About a Verilog code for digital Sigma-Delta modulator

    take a look at my code, i think it is correct
  13. S

    Can I increase the gate length in my layout?

    yes, it works it will be better if you have the correlation data from fab or, to make yourself more confident, do post simulation
  14. S

    telescopic with folded cascoded gain boosted

    gain boosted problem could you show your circuits? no improvement after the gain boost amps are inserted? does it mean the two amps don't work at all? could you check your DC operation point?

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