Can I increase the gate length in my layout?

[shsharifm]

Hi
I designed a layout of a dynamic latch with virtuoso in 90nm. In my circuit to increase the delay I increased the gate length of two of the transistors in the cell. The virtuoso simulation worked perfectly and the cell has acceptable delay because of the bigger gate length. Today, somebody told me that this can not be trust-able and increasing the gate length can make the device acts as long channel device and although the simulation result show me the delay, I shouldn't use this method. Can any body please tell me why? I can not get it. Why in virtuoso or any layout designer tool I can not design a layout in 90nm with a nmos and pmos bigger than 90nm gate length?

 

[erikl]

Of course you can do that.
A possible restriction (both for W & L) concerns the validity of the simulation models. That is why some foundries' PDKs restrict not only min. but also max. values.
Generally, the simulation models are sufficiently accurate for L ≤ 20*Lmin and 1/20 ≤ W/L ≤ 20 . Don't worry as long as you stay within those limits!

 

[strennor]

yes, it works

it will be better if you have the correlation data from fab

or, to make yourself more confident, do post simulation