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Hi there,
I am trying to find a commercial chip that is digital controlled binary weighted capacitor array. I can use it with a digital control circuitry, to tune the cap value as I need.
Is there one kind of this capacitor array? I dont know its professional industry name, so it is hard to...
Thank you for your quick reply, that might work. but could you please give more detail info? for example, if I use a SAR logic or just a counter to control the cap array. how should I define the digital code into parametric analysis?
thank you
Hi guys,
In my circuit, there is a digital controlled capacitor array, I would like to evaluate the AC response (of the entire circuit) change due to capacitor array's capacitance value change. Meaning that for each capacitance value controlled by digital controlled cap array, I need to perform...
I am trying to write a verilog A code for a SAR logic block, however, I met the syntax errors "Encountered a contribution statement embedded in an analog event"shown in below. the following is part of the entire code where error occurs. This code works pretty good with 0.5um CMOS, but when I try...
Thanks, but I am not using code to generate ideal comparator, I am using vcvs to edit parameters as pPar("parameter"), any idea then?
thanks again for you reply
Hi all,
I am creating ideal Parameterized comparator cell, which has parameters of voltage gain, positive supply, negative supply, However, After create the symbol for the comparator, when I instance that comparator to a new schematics, when I assign a value to the positive supply area, the...
Thanks,
let me show you part of the schematics, from the image, fixed R, C is unknown, based on algorithm, I need to tune 10 bit cap array and 10 bit Resistor array to find the unknown R C on top of the schematics, the circuit is excited by AC signal from 1MHz to 100MHz, in this case, I dont...
I need the min resistance around 10ohms, but also this resistor ladder will be used in high frequency application, the parasitic caps associate would be also problematic.
Thank you so much for the suggestions,
However, I have considered the series connected scheme with switch to short different resistor to get linearly increased resistance along with digital codes. however, this scheme would mess up the resistance values since the turn on resistance of each MOS...
Hi there,
i am trying to design a 10-bit binary weighted resistor ladder, the ladder is switch controlled, and can get binary weighted values from R, 2R, 4R,..... 512R. And it can be sumed based on a SAR logic control. Is there such a ladder? I just want from two node, I can get different...
Hi,
Any idea on how to create a "project" in cadence with several participants, so the participants from different location can work on the project asynchronously
Thanks
I saw some simulation bench. There are vcvs placed between the circuit and a supply, anyone know the reason? is it just like a buffer? but if it is a buffer, in cadence, supply source are ideal, why need buffer then?-
I added a image to this thread, what is the specific reason for the vcvs in...
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