Verilog A error: Encountered a contribution statement embedded in an analog event

[storyee]

I am trying to write a verilog A code for a SAR logic block, however, I met the syntax errors "Encountered a contribution statement embedded in an analog event"shown in below. the following is part of the entire code where error occurs. This code works pretty good with 0.5um CMOS, but when I try this code in a totally different process, then it gives the errors which does not make any sense

analog
begin
@(initial_step or initial_step("dc", "ac", "tran", "xf"))
begin

V(aout) <+ 0;

for (i = 0; i < `NUM_BITS; i = i + 1)
begin
vd = logic_low;
vnd = logic_high;
end

generate i ( `NUM_BITS-1, 0)
begin

V(dout) <+ vd;
V(ndout) <+ vnd;
end

currentbit = `NUM_BITS-1;
started = 0;

end

@(timer(startdelay))
started = 1;

@(cross((V(clk)-vth),1))
begin
if((started) && (currentbit >= -1))
begin
// $strobe("current bit is %d", currentbit);

if (currentbit > -1)
begin
vd[currentbit] = logic_high;
vnd[currentbit] = logic_low;
end

comparator = (V(comp_in)-vth) * comp_pol;
// $strobe("Comparator minus threshold is %g", comparator);
if ((comparator > 0) && (currentbit < (`NUM_BITS-1)))
begin
lastbit = (currentbit + 1);
// $strobe("changing back last bit %d", lastbit);
vd[lastbit] = logic_low;
vnd[lastbit] = logic_high;
end

currentbit = currentbit - 1;

end
end

generate i ( `NUM_BITS - 1, 0)
begin
V(dout) <+ transition ( vd, tdelay, ttransit );
V(ndout) <+ transition ( vnd, tdelay, ttransit );
end

ana = 0;

for (i = 0; i < `NUM_BITS; i = i + 1)
begin
if (vd == logic_high)
begin
ana = ana + pow(2,i);
end
end

ana = ana / pow(2,(`NUM_BITS));

V(aout) <+ transition ( ana, tdelay, ttransit );

end

endmodule

`undef NUM_BITS

 

[JoannesPaulus]

I doubt this code would work in any process technology since verilog-a is process independent...
At any rate, you can't have contribution statements (i.e. "<+"), for instance, in an initial block. Just follow the line numbers and modify the code accordingly. This code might require some minor re-writing...

 

[storyee]

I doubt this code would work in any process technology since verilog-a is process independent...
At any rate, you can't have contribution statements (i.e. "<+"), for instance, in an initial block. Just follow the line numbers and modify the code accordingly. This code might require some minor re-writing...

Can you show an example about what you talked?like how to avaid that error by rewriting code