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Usually 3rd party related stuff are NOT to be discussed owing to IP infringement/Copyright. For all these questions, I would recommend contacting directly the concerned firm.
I would think that POLY based resistor would be apt too even though its silicided.
Irrespective of the material chosen i.e. WELL/POLY, it is recommended to do more than the minimum width owing to etching and granularity/deposition undersize./oversize. For example, 0.18um poly might be around...
One should be able to dump the Netlist from the simulator. Review the model call for the device.
For different model call, change the model path in the simulator and redump the netlist for confirmation.
Usually in the log file there should be two sentences that shows the physical location/layer "dots" are. Usually the mask perp is good enough to disregard the "dots" but one can also remove them from the layout. If its playground, then choose nil for a parameter in the avParameters section...
Usually for PDK interviews, one does need to know something about what PDK is but is not essential. What I would say is a must is : Fab, little bit design (product definition to fab), layout and software development knowledge. Rest is usually learnt hands-on.
All the best.
Re: drc problem in cadence
#1:
Remove the .drc.Last.State file. If it is lvs, .lvs... or rcx is .rcx... and qrc is .qrc...
#2:
Sometimes, the variables are defined in the condition statement but never predefined in assignment statement.
guard ring
As long as the connectivity and the functionality of the circuit is not compromised, I think you can connect rings with ESD ground. Infact, it will now have more surface area of large discharge.
SRivats
Switches are like If-then-else loop inside the DRC rules file. So if you have options like multiple top-level metal layers, then you need to put it. Or you can two layer definitions where you would read either DFII or GDSII. It depends on what you want and you wouldnt find any "specific" docs...
ESD Question
I dont agree at all with not having the ESD protection because presence of "good" output buffer is at best secondary protection inspite of following all ESD rules.
Anyways, if you do follow the ESD rules, have you seen its frequency response in the desired range for the...
junction breakdown calculation
If its linear, and you have two points, namely, thinner doping and thicker doping values, make a line and find its slope. X-axis is the distance. Y-axis is the doping profile.
I am not too sure about my answer, but the reason I think its not a bad method is...
cmos od layer
OD2 -> Another Oxide Diffusion usually thicker than OD.
Seen usually in dual-voltage CMOS process.
Presence of OD, OD2, PIMP, NIMP seperately is to allow as many voltage nodes as possible in a given CMOS process. You can also have OD3, which can be low-leakage device OD layer...
I think in your inductor layout, you have your NWELL floating underneath it. There are few other compoenents (like passivation opening) where NWELL is left floating. Nothign wrong with it (usually). I think you need to remove the inductor-ovelapping-NWELL from the whole collection of your NWELL...
Re: assura problems?
I think I can help but I need the log file. Save it and send to me. I thikn it is not able to read the layout and create vdb file which is the interna ldatabse file that is used during the DRC run.
Also send me a screen capture of your DRC GUI.
Srivats
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