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Recent content by srik

  1. S

    What's the function of phase_lin statements in VerilogA?

    vco veriloga The comments above the blue lines explain its purpose! Those lines are to prevent phase ramping to very high value with time.This is because the simulator cannot deal with a very large numerical value. So it wraps the phase to +/- 2pi. srik
  2. S

    Spice code for IC741 OpAmp

    spice code for opamp hi, look up for the circuit in Gayakwad textbook. look for the region of operation of all the devices. BTW, which spice models do you use for the transistors?
  3. S

    Looking for tutorials on SPECTRE RF

    SPECTRE RF Do not miss the forums on h++p://www.designers-guide.com. This site is run by the guy who wrote SpectreRF for Cadence. It is very valuable.
  4. S

    How to do this in IC5?

    oppoint .scs yes, to plot gm (and others) as a function of input voltage, some parametric analysis is needed. I guess it does not happen at the click of a button :(
  5. S

    How to do this in IC5?

    spectre dc annotate plot of gm can be got by running a small signal analysis and plotting id/vgs (both id & vgs are small signals) using calculator function of IC5. srik
  6. S

    Who can simulate phase noise of VCO by SPICE?

    hspice phase noise hey flyinspace look at https://www.designers-guide.com/ look at the forums section. SPICE-like tools cant be used for this purpose, as they are not capable of determining Periodic Steady State solution of oscillators. SpectreRf can be used for your purpose.
  7. S

    Redhat 7.3 crashes when booting!

    /etc/lilo.conf
  8. S

    Any Free Screen capture tool for Linux

    You can use GIMP to aquire screen captures. You can play with images with this tool. https://www.gimp.org/
  9. S

    Bad news for US Engineers

    To Guestsy: Talking about the long run, I think in the long run the people who lacked knowledge and culturally different, can gain knowledge and be culturally compatible (if they already are not, and if it is a big barrier to a project's success ).... Come on, how difficult is it gain `specific...
  10. S

    Acroread 5.06 can not work on RED HAT 9.0?

    unset LANG environment variable
  11. S

    VLSI front end engineer (digital)

    HI, This position is based in India, Please PM me. Immediate requirement for a VLSI Front End Engineer with a good knowledge of RTL coding and ASIC synthesis with 3+ years of experience. srik
  12. S

    Immediate openings in Digital Backend design

    This position is based in India: Please PM me We have a urgent requirement for Strong Digital(Back-end) person for the upcoming project. Skills Required: Atleast 4 years of continous experiance in working for Digital P&R, Strong Process knowledge, exposure to work with...
  13. S

    NCSU kit and HSPICE models

    www.mosis.org
  14. S

    NCSU kit and HSPICE models

    LEVEL=11 for bsim3 mosfet models in spectre. Replace LEVEL=49 by LEVEL=11 in the spice models.

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