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Recent content by snake0204

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    sending data to a hardware acclerator

    Thanks for the response, my hw acc does not include any DMA. The block is interfaced to a OCP bus (to enable design reuse we use OCP bus interface for all our blocks). So in effect there is a PLB-OCP bridge and all the hw acc sit on this OCP bus. So what we need is probably a DMA sitting on the...
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    sending data to a hardware acclerator

    Hi Guys, I need a little advice here with Xilinx XUP board. I developed a HW accelerator for a video processing task. I write pixel data along with some additional data word by word to HW accelerator through software, but this writing data through software is slowing the system down, in the...
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    Warning XST: 2677 - Node of sequential type is unconnected in block

    warning:xst:2677 That warning is caused by lot of things..... One main reason is if your outputs are not connected..ie if you are not reading the module outputs the ise optimisation step removes all signal inside your block and fire a 2677 warning... check the module outputs S
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    Problem with simulating PAR model in Modelsim

    Re: Simulating PAR model Thanks for the reply.... I don't have any problems with my functional simulation it works fine. I am trying to simulate the PAR model just to make sure every thing works. I included all the simprim unisim simulation libraries form Xilinx thats not a big problem the...
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    Simulating post place and route modle

    Thanks for the help....i placed a global period constraint for the model but when I simulate the PAR model, non of the input signals are entering the input registers. I placed the pad to setup and clk to pad constraint as well but it is not helping. I attached the wave from modelsim. The third...
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    Problem with simulating PAR model in Modelsim

    Hi everyone, When I try to simulate a PAR model of my design it is not working. I am using xilinx ISE to do place and route and modelsim to simulate the model. I constrained my design to run at 100mhs that is placed a global constraint on my block. Here is the code for my simple adder circuit...
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    Simulating post place and route modle

    Hi all, When I synthesize my VHDL model XST synthesis reports says that the design can run at some 215Mhz, and when simulate the behavioral model (at 100 Mhz) every thing is fine. But when I try to simulate the post place and route model with the same test bench at 100 Mhz it not working at...
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    smoothening filter for entopy error

    Re: smoothing filter Thanks for the response! cheers snake
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    smoothening filter for entopy error

    smoothing filter Hi Everyone, I have a question regarding smoothing an arbitrary signal. The signal is a entropy error rate which indicates the amount of information contained in dark and bright pixels in an image. The EER helps to find out the illumination in the scene. The problem is the...

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