Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have used two out of phase pulse inputs with the opamp configured in unity gain configuration as in the attached picture. where all R's=1K,then i plotted vout1-vout2 and taken the slope of it,which gives a value of 3e10,it gives almost the same value when i calculate it with delta cursor.Does...
In analog lib ,you will see "Vsin" ,put it in series with the input voltage source V3 at vmais;
Vmenos=1.2V DC only,remove the feedback loop.
For Sinusoidal source ,take Amplitude=Magnitude=10mV,Freq=according to your application(e.g. 1M).
Now do AC analysis,sweep frequency from 1 to 1GHz in...
Hi
I am designing gain boosted Opamp.I don't know much about Noise in analog circuits.Can anybody tell me the simple procedure to find the Noise in this opamp.
Is it necessary to take the values of width and length to be a multiple of default minimum value.e.g default W=120nm and length=100nm for gpdk90,then can we take the width of a MOS equal to 140nm or it should be either 120/240/360.......
yes,the minimum value of W is 120nm and L=100nm for 90nm technology in Cadence gpdk90.I m using 120nm width and 800nm length for some transistors.Is it appropriate to use this much high value of length.
Is it possible to have Aspect ratio of less than 1 in analog circuit design i.e. W<L
I am designing gain boosted Operational amplifier in Cadence which has gain of 76dB but the W/L ratios of many transistors are <1,is it allowed to have W<L?
i am designing a gain boosted amplifier and the gain is not high.all the transistors are in saturation.i am using simple differential amplifiers as auxiliary amplifiers.The gain i am getting is 76dB with UGF of 700Mhz but the UGF<PCF so the system is unstable even in open loop configuration,It...
how to calculate channel length modulation constant lambda in cadence gpdk90nm.
i calculated it by gds/id and also by pclm parameter( but the values are 1.5488 and 1 which seems to be very large) as compared to 500nm technology which is given in RAJAVI's book.
if u have calculated plz tell me.
Hi m designing a telescopic opamp with single ended output and the swing is only 600mV with a supply of +/- 500mV.The ac analysis shows a d.c gain of 52 db i.e.498.
I given an input of 10mV sinusoidal wave so the output should be 4.98V(as it is showing in ac analysis) i.e .the output should...
increase the length of load transistors to increase their output resistances .
Av=gm1((ro1.gm3.ro3)||(gm5.ro5.ro7))
Do not incerase the length of M1-M4 much as it will increase the capacitance.
Try this:
M1,M2=240,400n
M3,M4=600,400n
M5M6M7M8=960,800n
M9=240,400n
M10=3.6u,400n
Iref=20u...
i am designing two stage miller compensated opamp which has differential inputs vinp and vinn and single output vout.the first stage is simple differential amplifier and second stage is common source which is compensated by miller capacitor and an NMOS(in triode region) .
My question is:
How...
I created a schematic of NAND gate and then generated a symbol for it.
When i use the symbol in other schematic where i apply the inputs A ,B,Vdd and Gnd,it shows an error"The non global net vdd is shorted to global net vdd".
Sometimes the schematic window disappears when i click on SIMULATION...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
