Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

cmos 2 stage opamp designing in cadence

Status
Not open for further replies.

shitu_khairnar

Newbie level 4
Joined
Oct 13, 2010
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
I want to design CMOS 2 Stage OPAMP in cadence in 0.18 µm. plz give me an example of it. can anybody help me?
 

The file attached is one of the best sources of information for two stage op-amps.
I used it in a student project of mine. It worked vary well.

Enjoy!
 

Attachments

  • tutorial - two stage.pdf
    1.5 MB · Views: 298
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top