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what does this mean?
"Last time I asked about this I seem to remember the figure 5um being kicked around for the region of substrate destruction."
Also, can you make connections from the backside of the chip?
My mount hole is too small :(
Is there an attachable standoff? a standoff that doesn't require holes on four corners of the PCB? What do you call these things?
I guess I could drill the PCB to create the hole but I really don't want to apply any mechanical force to it.
Thank you
I need to cut and reconnect a wire in my digital logic.
the distance is short, just about couple um.
However, it has to reach all the way down to metal 1.
Does anybody know what the yield rate is for doing fib on the lowest metal layer?
Can anybody recommend a good company for this task?
Thanks for keeping up erikl.
The PDK mentions not to route anything under the mimcap structure.
I think(?) this may be due to the fact that the cell models substrate parasitic cap with the assumption that there's no metal underneath.
Nevertheless, since the PDK says not to do it, it makes me...
Thanks,, both of you have recommended to put regular metals (1~6 to path density) underneath the unit MIMCAP
this is kinda scary to me :( I just feel like it's gonna drop the linearity... argh..
I guess I gotta decide .. hm..
Hey guys,
I have couple MIMcap arrays for my design.
I have very little routing going through the MIMcap array and if I run chip-level DRC, it gives me density errors.
How do people get away with this error? Do you waive them?
The PDK shows that nothing should be routed underneath the mimcap...
Hi guys,,
what's the usual mos decoupling unit cap size you use for your onchip power decoupling?
I understand that depending on the W/L size, gate resistance changes and there's an optimum size to de-Q inductance ringing. I'm in a real crunch and unfortunately don't have time to think through...
Hi, I'm using an momcap from the PDK
It has a poly layer throughout the bottom(below M1 layer of course), which I connect to ground.
This is equivalent to the third terminal in the schematic 'symbol' view.
Howver, I'm not sure what to do with the bottom nwell.
It is floating and when I do LVS...
Hi,
I'm trying to shield the mimcap from the substrate. This is for my ADC design.
I have two-options. first is to put NWell beneath the cap. the other one is to put deep nwell beneath it.
Obviously, deep-nwell is better. But is it really necessary to shield it with a deep-nwell?
What is the...
I'm not sure what you mean here.
If I stack them, then the layout get vertically long.
But the two boost amps are different (one is PMOS folded, other is NMOS folded) and if I place them at the sides of the main opamp the symmetry is not maintained. What do you mean by repetition?
Thanks again~
Do you have any suggestions on how to layout an Gain boosted Amp?
I'm not so sure if I should place the two differential gain enhancing amplifiers in a stacked fashion between the PMOS and the NMOS tail current source of the main amp. Or I could place the gain enhancing amp on oneside of the...
I am controlling the bulk voltage of an NMOS to reduce threshold.
Inevitably, there will be a positive voltage across the PN juncion.
I will keep this voltage level lower than the diode 'on' voltage of approx .6V
My main concern is the leakage through the substrate with this configuration.
I...
Is there a way to level shift by 0.1V?
It obviously cannot be a source follower since VGS>0.1V.
And I'm not interested in cascadeing a PMOS source follower and a NMOS source follower to obtain voltage difference.
Capacitive level shifting is also not an option...
Is there anything out there...
Hi, would it be risky to bring a 500MHz single-ended clock into the chip.
I need it as the sampling clock for my ADC design.
I wondering if this should be done differentially using an off-chip balun.
If you have experience or reference, pleaset let me know.
Thank you.
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