simulating leakage from substrate biasing

[sharkies]

I am controlling the bulk voltage of an NMOS to reduce threshold.
Inevitably, there will be a positive voltage across the PN juncion.
I will keep this voltage level lower than the diode 'on' voltage of approx .6V

My main concern is the leakage through the substrate with this configuration.
I have tried varying the bulk biasing via ideal voltage souce connected to the the bulk and probed the current flowing through this voltage source.
Is this an accurate of way predicting the leakage coming from the PN junction?
It shows ~pA of current for low level foward biasing and quickly goes into nA and mA as the forward biasing increases.
This is for 65nm processing node.

Thank you.

 

[erikl]

Your results seem ok. They are just as good as the model describes them.