bringing in a 500MHz clock signal into the chip

[sharkies]

Hi, would it be risky to bring a 500MHz single-ended clock into the chip.
I need it as the sampling clock for my ADC design.

I wondering if this should be done differentially using an off-chip balun.
If you have experience or reference, pleaset let me know.

Thank you.

 

[apolama]

Hi,
It would not be risky to do that.

most of the clock source provide differential output.

 

[RCinFLA]

If you only need it for ADC clock would be better to include a PLL to boost freq. Putting a single ended 500 MHz into a chip from outside will likely have jitter degradation. Also would have poor duty cycle predictability. Jitter performance for ADC is usually strick and poor jitter means poor ADC noise floor.

Power drain for a single ended rail to rail driver would also be high. LVDS yields lower jitter and better noise immunity.


Look over Analog Devices data sheets for similar speed ADC chips.

 

[dick_freebird]

You can use a capacitor-blocked, auto-biased inverter
to take a ground referenced low amplitude signal and
gain it up to logic levels, provided that your inverters
have remaining gain (I'd say you need no more than a
200pS rise and fall time, 20-80% of VDD, with some
useful fanout load).

Some issues include noise / phase noise on a low
amplitude sinusoidal signal, and unusual startup action
could be a possibility if the clock rides on some
common mode that moves at power-up and jacks
the inverter bias-point until settled.

I've seen CMOS dividers with this kind of input run
past 10GHz but my personal work has used ECL input
buffers and only run up to 1GHz. The choice is most
likely determined by the source, not the destination -
what does a "good enough" clock source, or the one
you get to use, look like?

 

[FvM]

If you only need it for ADC clock would be better to include a PLL to boost freq. Putting a single ended 500 MHz into a chip from outside will likely have jitter degradation. Also would have poor duty cycle predictability. Jitter performance for ADC is usually strick and poor jitter means poor ADC noise floor.

I doubt, that an on chip PLL without external filter and oscillator components will be able to improve jitter. It will primarly copy the input clock jitter and add some on it's own. I agree about the duty cycle aspect, that's why some ADCs are using internal clock stabilizers. But they add a small jitter amount though.

A LVDS full rate clock input would be probably the best option. Considering ground bounce produced by the ADC chip, even a differential clock input that's single ended connected off-chip promises some improvement of clock signal quality. It's also not unusual to connect a single ended clock signal through AC coupling to a differential input with internal biasing.

While the encode clock should be supplied directly, high speed ADCs are sometimes provinding a PLL for digital output timing. But that's a different topic.

 

[Nishant Jadav]

Need,
Have anyone Resistor and capacitor single ending circuit for generating 500MHz frequency for ADC 0809.

And also want C code for interface ADC with microcontroller 89v51RD2 for display three channel analog output on LCD..
Please..

 

[FvM]

generating 500MHz frequency for ADC 0809

Are you joking? Or did you mean 500 kHz?

 

[Nishant Jadav]

sorry it is 500khz..can you help me..

 

[FvM]

It's not actually related to this thread, but how about a 74HC14 schmitt trigger oscillator?

 

[jgk2004]

I think a 500MHz CLK on chip is risky since you need a low jitter CLK for your ADC

I would recommend using a high speed generator which outputs a sinewave, then having on the PCB a balun that converts your sinewave to fully differential, then run both onto your chip. Then spend power in a fully differential comparator to rectify onchip to create your CLK. (This power within the comparator is NOT including in the ADC FOM in top publications and is consider like using a PLL, therefore just spend alot to make sure your jitter is low) This will provide a low jitter clock.

I did this with my last ADC up to 1GHz, while having a jitter well below 1ps RMS. Then ofcourse later on in the design a PLL would need to be implemented.

Hope this helps,
JGK