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Hi,
when doing synthesis with designware components (IP) and rtl files.
problem:
1)when doing liniting check it reporting LATCH based in Designware component
2)when doing synthesis it with same code there is no latch forming, so what happen designware component in when...
timing
hi,
I have attached word file related to timing
1)What kind of timing violations for the ckt diagram.
2)In that circuit for CLK
*if frequency is 100 Mhz then what kind violations occurs
*if frequency 10 Mhz,then what kind violations occurs
3)if i go 100 Mhz or...
hi,
1) what is mean by powergrid?
2) In low power design the number of powerswitchs where we get for our design?
3) what are inputs parameters require for block level powerplaning?
In rtl passing value is not allowed, you are using ctrlList.sram[addr1] <= 0;
you are passing value to sram[addr1] to zero it is only used in testbenches.
Regards,
Ravi.
Hi,
How to create constraints for 200 Mhz design.
1)for calculating input/output delay,clock_uncertainty,clock_latency there using some percentage(%) of clock(200Mhz),where this percentage we are getting.
2)and also for max_transition ,max_capacitance how to calculate.
create_clock...
Hi,
In Physical design we are implementing the lower power tech: Multi VDD, Power Gating,
Multi Vt, Clock gating.
EX: I have two block A, block B. I want to work block A to 1.2v and block B 1.0 v Multi VDD tech.
To implement this Multi VDD where i have to specify?
Hi,
After completing floorplan and powerplan for full chip ,what are the steps to partition the blocks from full chip.
eg:push down,partition pins etc
Regards,
Ravi.
Hi,
i have macros ,for that macros around some space require to aviod congestion. we have to put placement blockage no std cells to place that area. Any calculation is there for spacing?
Regards,
Ravi.
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