seeravi
Member level 1
Hi,
when doing synthesis with designware components (IP) and rtl files.
problem:
1)when doing liniting check it reporting LATCH based in Designware component
2)when doing synthesis it with same code there is no latch forming, so what happen designware component in when doing synthesis.
Regards,
Ravi.
when doing synthesis with designware components (IP) and rtl files.
problem:
1)when doing liniting check it reporting LATCH based in Designware component
2)when doing synthesis it with same code there is no latch forming, so what happen designware component in when doing synthesis.
Regards,
Ravi.
