synthesis constraints

[seeravi]

Hi,
How to create constraints for 200 Mhz design.
1)for calculating input/output delay,clock_uncertainty,clock_latency there using some percentage(%) of clock(200Mhz),where this percentage we are getting.
2)and also for max_transition ,max_capacitance how to calculate.


create_clock -period _ ? [get_ports clock]
set_input_delay -max _? -clock clock [all_inputs]
set_input_delay -min _? -clock clock [all_inputs]
set_output_delay -max _? -clock clock [all_outputs]
set_output_delay -min _ ?-clock clock [all_outputs]
set_clock_uncertainty -setup _? [get_ports clock]
set_clock_uncertainty -hold _? [get_ports clock]
set_clock_latency _ ?clock
set_clock_latency -source _? clock
set_critical_range _ [current_design]
set_max_transition _? [current_design]
set_max_capacitance _? [current_design]

Regards,
Ravi.

 

[jbeniston]

Max input/output delay will depend on the circuitry outside of your design.

 

[rca]

set_max_transition/capacitance may modified if you don't trust (or if not define) in the std cell library

clock uncertainty depend on the margin you want to have, or how much you want to push the tool to safe your design.

clock latency define the model of your clock generator, I not sure it was a must

 

[phoenixfeng]

I think you need study basic concept about synthesis
Constraints contain environment constraint and functional constraint, 200MHz is just clock constraint

 

[hari24rock]

40% of your clock period for input & output delays.