How to implement Multi VDD ?

[seeravi]

Hi,
In Physical design we are implementing the lower power tech: Multi VDD, Power Gating,
Multi Vt, Clock gating.

EX: I have two block A, block B. I want to work block A to 1.2v and block B 1.0 v Multi VDD tech.
To implement this Multi VDD where i have to specify?

 

[randyest]

Re: power planning

Oh boy that's a huge question. Do you have experience with low-power backend flow? Which tools are you using? If Synopsys, you need to make a UPF (Universal Power Format) spec file. If Cadence, you need to make a CPF (Common Power Format) spec file. They are similar, but different syntax, and they both specify each power domain, the library cells used for each power domain, the voltage ranges for each domain, and the isolation cells and level shifters for each domain.

It's not a simple question to answer, but maybe that will get you started.

 

[hiral.kotak]

Re: power planning

Hi,

Multivoltage cells can be used in multi voltage design (Mvdd) in which there are different voltage domains. for e.g.
Special cells are required for implementing a Multi-Voltage design.

1. Level Shifter
2. Isolation Cell
3. Enable Level Shifter
4. Retention Flops
5. Always ON cells
6. Power Gating Switches/MTCMOS switch

Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS's are very simple whereas L2H LS's are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.

Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'. In a nut-shell, an isolation cell is necessary to isolate floating inputs.
There are 2 types of isolation cells (a) Retain "0″ (b) Retain "1″

Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.

Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be 'always_on' and hence special care must be taken to synthesize/place/route them. In a nut-shell, "When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used".

The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.

Always ON cells: Generally these are buffers, that remain always powered irrespective of where they are placed. They can be either special cells or regular buffers. If special cells are used, they have thier own secondary power supply and hence can be placed any where in the design. Using regular buffers as Always ON cells restricts the placement of these cells in a specific region.

In a nut-shell, "If data needs to be routed through or from sleep blocks to active blocks and If the routing distance is excessively long or the driving load is excessively large, then buffers might be needed to drive the nets. In these cases, the always-on buffers can be used."

Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt gates are used for speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in various different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into every standard cell, or they can be used to switch off a large design block of standard cells.

Hope this will help you.

Thanks.

HAK.

 

[seeravi]

Re: power planning

Hi,
In which stage we have to start CPF or UPF.

RTL stage or Synthesis stage or PNR stage.



Regards,
Ravi.

 

[rca]

power planning

you should also used the CPF or UPF at simulation level, to inform the simulator the power dimension of your design, in this case, the simulator, will force the signal to X when the module is power disable.

Of course, the complete backend flow need to be aware of the power constraint, synthesis, P&R, LEC, ATPG, STA.

 

[raghurama86]

Re: power planning

If your design has a power down block then you will have to use all the above 6 special cells if there is no power down block then you can only use

1. Level Shifter
2. Isolation Cell
3. Enable Level Shifter

because you are in physical implementation team you wil get a UPF file from the synthesis team. u will not b doing a UPF file all by u r self, you can try to load the design and dump UPF file it might work.