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Can some share with me some material on :
1. Example of glitch
2. How to avoid glitches on clock domain crossing path ?
3. Issues due to glich propogation in CDC :roll:
Can some provide information on :
1. what is glitchy logic ?
2. How RTL code when synthesized will be converted in to glitchy logic ?
3. Various RTL code that can be converted to glitchy logic ?:???:
Example of shoot through in RTL :
p_comb: process (mclk)
begin
mclk1 <= mclk;
end process;
p_sync1: process (rst_n,mclk)
begin
if rst_n = '0' then
data_int <= '0';
elsif mclk='1' and mclk'event then
data_int <= data_in;
end if;
end process;
p_sync2: process (rst_n,mclk1)
begin
if rst_n = '0'...
If we know that about CDC crossings in design . Do you see that we can take advantage of such reports during the synthesis (may be on the crossing synthesis tool is trying to put more effort to meet the timing etc)?:?:
regards
sakshi
Yes u are right that code mentioned below may cause infinite loop in simulation
always@(b or a)
begin
c=a ;
a=b;
end
My question is then to avoid this situation , we should write code like this:
assign c=a;
assign a=b ;
Are two codes equivalent ?
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