glitchy logic in Netlist

[sakshi gupta]

Can some provide information on :
1. what is glitchy logic ?
2. How RTL code when synthesized will be converted in to glitchy logic ?
3. Various RTL code that can be converted to glitchy logic ?:???:

 

[rca]

glitchy means generate glitch. Combinational logic could generate glitch, like "a=5", if a is code on 4 bits, the 4bits do not change at the exact (ps) time, and so the comparaison logic could generate a 1 (during very few little time) instead generate a 0.