[SOLVED] Warning reported by design compiler while synthesizing RTL

[er.akhilkumar]

Hello All,

I am synthesizing a simple logic in vhdl which is following:

PORT(
A : std_logic_vector(15 DOWNTO 0);
B : std_logic_vector(15 DOWNTO 0);
C : std_logic_vector(15 DOWNTO 0);
D : std_logic
);
BEGIN

C <= A WHEN D = '1' ELSE
B;

END

While synthesizing the above logic DC Shell reports following warning:

Warning: In design port A[15] is not connected to any nets
Warning: In design port B[15] is not connected to any nets

Can anyone solve this out?

Thanx

 

[tariq786]

I don't know VHDL but should n't this be D == 1 rather than D = 1

please correct me if am wrong.

 

[er.akhilkumar]

No tariq786, it should be D = 1 as in VHDL equiality is checked by single equalto operator "=".

 

[kornukhin]

If this design is not the top level and during instantiation C(15) left unconnected (unused) then DC can cut A(15) and B(15) as unconnected inside module.

 

[sakshi gupta]

Yes if D will be unused, it will optimize A & B as these are unconnected

 

[er.akhilkumar]

But Sakshi as you can see in the post, D is used.