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Re: ASIC Design Flow
Read a book? Google "ASIC design flow tutorial"? Search this forum? For example, in the thread right under yours is a link to a design flow tutorial pdf:
In addition to koggestone's great summary, clock buffers sometimes have input and output pins on higher metal layers to avoid the need for vias in the root clock distribution network. Normal buffers have pins on lower layer like metal 1. It's better to keep clock routing on upper layers...
Am I missing something? Why do you think SDF annotation has anything to do with an encryption problem?
According to his error message, vcs is saying it can't decrypt a module (some primitive cell.) Even if SDF annotation failed (which we have no evidence of) vcs obviously can't decrypt...
Thanks for the reply. I'm a little confused though - you say it maybe hard to get a pure translation to work, but it sounds like your tool is a pure translation tool? Did I miss something.
If you wouldn't mind addressing my other questions I would be willing to review your answers and the...
Eh, it's a semantic terminology thing that not everyone uses the same way.
To me, power rails are usually horizontal METAL1 grids that connects directly to each standard cell's VDD and GND pins.
Power stripes are the METAL2 - METALX (upper layer) larger, fatter, higher-pitch (bigger spacing)...
I made a nice chip that is effectively a frame buffer with two clock domains and a bunch of buffer space (kind of like a FIFO,) and some special fancy control features and interfaces.
My chip has bout 150 I/O pins, a lot of DRAM, and roughly 5 million gates of logic. It works very well and...
D flip flop
I usually think of DFF as a sequential element or cell which is used to make a sequential circuit. Sequential circuits, as opposed to combinatorial or combinational circuits, are those with clocked storage elements like DFF (or TFF, or JKFF) or latches, or other memories...
It looks like your encrypted model was encrypted by a tool other than vcs. Maybe NCVerilog or some FPGA tool? In my experience encryption is tool-specific. Maybe ask your vendor / fab what tool they encrypted it with and see if they can re-do it for vcs? Sorry I can't be of more help.
I don't think encounter will calculate it for you. At least I have never found a way. I calculate manually based on cell count per domain, frequency, activity ratio, etc.
Annotating an SDF or not has nothing to do with an error message about encryption. Can you quote the exact error message? I maybe able to help if you can provide the details.
There are a lot of good threads here for interview questions if you search for "interview." But what is a "product engineer?" Sorry but I don't know -- it seems vague. What kind of product?
Oh, I see. Thanks for clarifying and sorry for my confusion. I don't know any automatic layout tool, but that doesn't mean they don't exist. Maybe so, but it seems like a complicated task compared to standard-cell placement tools and the like. Cell design is much harder for a computer I think.
pci related question
I don't think you give us enough detail to make useful comments. But I guess PCI-based DAQ card means you're making a PCI card that will plug into a PC for data acquisition? If so, it will probably need to be a target not a master. Right? The PC motherboard will be the...
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