wisemonkey
Junior Member level 3
Hi everyone,
I'm trying to go through vcs tutorial to get an idea of gate level simulation
I already have a synthesized design (on which I worked through last semester)
So now I'm trying to issue (since toshiba libraries have protected tag in them)
vcs +v2k -sverilog top.v tb.v design.postsynth.v -y ./lib/verilog/tc240c +libext+.tsbvlibp
However I still receive an error as bad encryption in one of library file and at token "protected"
Thanks for any suggestions![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
I'm trying to go through vcs tutorial to get an idea of gate level simulation
I already have a synthesized design (on which I worked through last semester)
So now I'm trying to issue (since toshiba libraries have protected tag in them)
vcs +v2k -sverilog top.v tb.v design.postsynth.v -y ./lib/verilog/tc240c +libext+.tsbvlibp
However I still receive an error as bad encryption in one of library file and at token "protected"
Thanks for any suggestions