Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by rakesh_aadhimoolam

  1. rakesh_aadhimoolam

    [info reqd] Nand flash channels and PCIe lanes meaning

    Can anyone brief on this please. Thanks
  2. rakesh_aadhimoolam

    [info reqd] Nand flash channels and PCIe lanes meaning

    Hi, Eg : The 89HF16P04AG3 is a single chip 16- channel NAND Flash controller with PCIe Gen3 x4 What does 16 channel here mean and what are these channels ? PCIe x4 means 4 lanes - so what does lanes here mean ? Can anyone give infor regarding this from an SOC perspective. Thanks
  3. rakesh_aadhimoolam

    [need]controller frequencies of video and audio applications

    Hi, We will be implementing H.264 & AC'97 audio codecs on FPGAs. We would like to know the controller frequencies as it is crucial for determining FPGA density and working frequency. Where can i find information on Working frequency of such applications Anyone who implemented such controllers...
  4. rakesh_aadhimoolam

    DDR2 contrlr runs at 78MHz on FPGA...why FPGA prototyping ?

    Hi All, I am presently working on DDR2 controller running at 78 MHz. It works fine in simulation as well on FPGA. But we have not achieved the real time target of 166MHz/200MHz. What is the use of FPGA prototyping here ? Why do we have to do it ? Thanks
  5. rakesh_aadhimoolam

    Palladium Emulation vs FPGA prototyping...your ideas ?

    Hi All, Can anyone state the differences between Palladium modeling and FPGA prototyping.... Their pros and cons...? Thanks
  6. rakesh_aadhimoolam

    High imped is used in TA of ethernet MDIOread transaction ?

    Can someone explain me this. it is very urgent. what is the importance of high impedance in read transaction why high impedance is used only in read transaction and not in write transaction. "The turnaround time is a 2 bit time spacing between the Register Address field and the Data field of a...
  7. rakesh_aadhimoolam

    MDC frequency in ethernet <= 2.5MHz ?

    Hello everyone, Can someone give a brief explanation that why is MDC frequency of ethernet is less than or equal to (<=) 2.5 MHz Thanks
  8. rakesh_aadhimoolam

    Wrap function importance in Cache lines ?

    Hello everybody, what is the function of Wrap in cache line implementations how is it implemented i know Wrap addressing - Wrap 8 word - x34 x38 x3c x20 x24 x28 x2c x30 but what is the importance of the Wrap function why is it used in cache lines Thanks Help Appreciated
  9. rakesh_aadhimoolam

    doubt regarding XGMII ...

    https://en.wikipedia.org/wiki/XAUI 10 Gigabit Media-Independent Interface (XGMII) is not a practical interface to use on a circuit board can anyone post the reason. Thanks
  10. rakesh_aadhimoolam

    Degree char not printing through RS232

    rs232 danish character set Hi all, i have degree character (º --- Alt + 167) in a file. but when i transfer it through RS232 port there is conflict in Degree character printing. anyone has any suggestions on how to print Degree character through RS232(Hyper terminal) Thanks
  11. rakesh_aadhimoolam

    List of vlsi companies in chennai.

    please check this document.....
  12. rakesh_aadhimoolam

    coding ....Design....errors in linting.....!

    Linting doubts : 1)what happens if reset is active high as well active low in same module.(reg are dependent on each other) module lint_test(clock, reset); input wire clock; input wire reset; reg [3:0] a; reg [3:0] b; always @(posedge clock or negedge reset) if (reset) a = 0; else a...
  13. rakesh_aadhimoolam

    FSM extraction...........?

    what does FSM extraction exactly refers to.. i am bit confused abt this. Thanks
  14. rakesh_aadhimoolam

    How to simulate Core Generated Model of Xilinx....?

    Hi.... Yesterday i generated a counter in Xilinx Core generator... How to simulate the same...is there any test bench model for that in Xilinx Itself... Thanks
  15. rakesh_aadhimoolam

    High Frequency Issues...?

    Hi... I have a doubt regarding High frequency issues.... what does short rise and fall time(high frequency) lead to in FPGA.... what does it do.... Thanks
See more

Part and Inventory Search

Back
Top