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Recent content by quy1001

  1. Q

    arcsin() implementation by FPGA

    arcsine, matlab Yes, I am wrong, LUT is the fastest way. My problem is about style of programming it make my design is slow. :)
  2. Q

    arcsin() implementation by FPGA

    arcsine look up table function arcsine_table(sin_val : integer range -32767 to 32767) return signed is --input is 16bit variable angle_value: signed(15 downto 0); variable sin_val_temp: integer range -32767 to 32767; --16 bit Q15 begin sin_val_temp := sin_val; case sin_val_temp is...
  3. Q

    arcsin() implementation by FPGA

    arcsin lookup Dear Mr. I have same problem with you now, I need to calculate the arcsin() function. I use a look up table, but it slow down my design. Do you have any way to apply arcsin() function, except LUT method.
  4. Q

    signed n in qformat Division

    Use IP core :)
  5. Q

    How can i generate a Pulse with a time = 35 ns

    How about using a DCM.
  6. Q

    A basic question on the FIR design in FPGA

    Yes, Matlab is good tool for design FIR and also IIR. The second think is you should have ability to handle Fixed point number operation. Then you can design any filter.
  7. Q

    Current converter with lag controller

    I am designing a current converter, for step motor controller. I use PWM converter with external MOSFETs. I control current by adjusting dutycycle of switching pulses. I feedback current by ADC, and comparing with Referent current (constant or sine shape). The error is input of P (or PI)...
  8. Q

    please help! vhdl square root

    Cordic is easy to solve that problem :)
  9. Q

    How operation of this circuit prevents bouncing problems?

    simple debounce circuit Is this circuit named Voting circuit.
  10. Q

    Can I open project done in ISE 7.1 on ISE 8.1?

    Re: ise 8.1 My opinion, we should upgrade ISE8.1. After that just open the old project, and fix the old project, if it requires.
  11. Q

    what is synthesizable

    Dear Friends. Use fixed-point number only for real number problem. It is enough for everything.
  12. Q

    really need help how to design square root!!! help me

    You can use IP core of xilinx, cordic, I think it is enough for use.
  13. Q

    help me! who has FPGA module schematic of Libertron Co., LTD

    Hi, everybody I have a FPGA module of Libertron Co., LTD. Its model is XC2V-MODULE V1.3 LBTN- XC2V-MOD-FF1152 But I lost its schematic. Who have that one? Please help me. If you have, could you rely or send me following my email address: tnga1001@yahoo.com Thanks so much.
  14. Q

    Simulation a logicore component

    ise modelsim warning vsim-3473 I already compiled all libraries of XilinxCoreLib by "Compile HDL Simulation Libraries" process. Also I map these libs. in file "modelsim.ini". Also I change properties of file ".xco" file in project to be "Synthesis/Imp + Simulation" But when i simulation my...
  15. Q

    Simulation a logicore component

    vsim-3473 component instance is not bound. I use Floating-point operator V2.0 in my design. When I simulation design in Modelsim 6.1b, there is no error, but the ouput of the wave window shows no output. The logicore component does not work in Modelsim. What is wrong? What should I check...
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