How operation of this circuit prevents bouncing problems?

[cmos babe]

I got this from ISE tutorial...can someone explain to me how it's operation prevents bouncing problems and why three flipflops were used ?

Thank you

 

[rogerliu]

debounce

The debounce time about 20ms normally, so the clock of D F.F. is about 100Hz,
three stage D F.F is guard time for deboune 20ms.

B&R,
Roger

 

[okguy]

debounce chip

Does anyone have an on-chip debounce without clock?

 

[dBUGGER]

debounce circuits

Hi,
Just check out if you can use a simple S-R FF for debouncing. I think that will be the simplest. Please correct me if i am wrong.

Best Regards,

 

[chandisciple]

debouncing circuit

hey u can get that very clearly explained in the logic design book by samuel jackson

 

[vijay_nag]

logic design book by samuel jackson

digital book by Tocci has given good explanation about debounce circuit. check it out

 

[JohnJ]

sr debounce

What that circuit does is samples the state of the switch over 3 consecutive clocks, if it is low for 3 consecutive clocks, then it is a valid transition. The idea is that if the switch bounces, it will sample a one which will take 3 clocks to clear the shift register.

The same algorithm is used a lot in software.

Add a 4 input AND gate, using the same 4 inputs, and hook the output of the AND to the J input of a JKFlipflop and the NOR output (bubble NAND) to the K input and clock to the clock of the JKFF you will debounce both make and break.

The trick is to make the clock period work with the bounce period of the input. The total of the number of clock periods you use should equal the stated max bounce period. (That is a guess, if anyone has another idea of the ideal clock period, please comment!) You can also increase the number of Flipflops (and gate inputs) to increase the debounce period AND decrease the chance of error. (If the input is bouncing, it seems to me that you have a 50/50 chance that middle sample will be a 0.)

I used that circuit in a quadrature decoder (rotory encoder) I just completed designing. It isn't bounce that's a problem with that (optical) it's that the max transition period is 30ms!

Added after 35 minutes:

Ooops! I just realized that the top wire in your schematic (input port to the NOR gate) is useless. It only monitors that the state of the input doesn't change during the propogation delay of the first FF. Since in the extended design (w/ JKFF) waits for the next clock to look at the logic, it adds another clock to the debounce period.

 

[quy1001]

simple debounce circuit

Is this circuit named Voting circuit.