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Recent content by preetam_24

  1. P

    DFT(DFT Advisor+ FastScan)

    Could anybody tell me how to do scan insertion in dftadvisor for latches. when I am performing full scan insertion it is only converting f/f in to scannable f/f. I am curiously finding solution how to do with rest of latches please send me solution as early as possible. In my design no of...
  2. P

    DFT(DFT Advisor+ FastScan)

    I am doing fullscan insertion of my design but my tool dftadvisor only converting f/f in to scannable f/f. In my design no of latches are more than f/f. It is not performing scan insertion for latches. So which command I should give so it will take care of latches. because in DFTAdvisor the...
  3. P

    DFT(dftadvisor+fastscan)

    I have performed synthesis of my RTL coding , after synthesis I performed formal verification there is no error. but when I am trying to do fullscan of synthesized code by DFT advisor(mentor graphics) it is not detecting whole flip flop. Out of 326 it is only convertring 294 F/F in to scannable...
  4. P

    wipro vlsi question paper

    could anybody send me recent question paper of wipro vlsi. so I can get idea how to prepare for placement. please send me as early as possible. this is likely to visit on 6 jan. I would grateful for same.
  5. P

    16 bits full adder implementation

    actually all this component will be treated as sequential element during synthesis but output will be gate level netlist
  6. P

    design compiler invoke for testability

    Error: Required argument 'file_names' was not found (CMD-007) when I did from design compiler
  7. P

    design compiler invoke for testability

    thanky dear it gave me some idea hopefully you will help me in future also.I will try definitely this method actually i have read yhis command somewhere else but but it was not clicked at that time regards preetam ---------- Post added at 08:17 ---------- Previous post was at 06:36...
  8. P

    design compiler invoke for testability

    what is this yadavvlsi ans who is this wouldd u please clear to me
  9. P

    16 bits full adder implementation

    please ask your friend and help me
  10. P

    16 bits full adder implementation

    i have synthesized code in Design compiler ,after that I have to perform testability could you give me essential commands for invoking Test compiler in synopsys. ---------- Post added at 19:36 ---------- Previous post was at 19:31 ---------- actually i was working on Mentor Graphics for scan...
  11. P

    16 bits full adder implementation

    actually first is fixed point adder and second is simple 128 bit adder these are ripple carry adder. i vave prob. could you tell me how to perform scan insertion in synipsys test compiler.
  12. P

    design compiler invoke for testability

    currently i am working on synopsys design compiler. I synthesized code very well after I have to move for scan insertion using synopsys TEST compiler. Is test compiler built in design compiler. could anybody tell me how to invoke/perform DFT(full scan+boundry scan) in design compiler...
  13. P

    16 bits full adder implementation

    module fxpt_adder(in1,in2,clk,result); input clk; input signed[32:0] in1,in2; output signed [32:0] result; parameter size = 33; reg result_sign, sign1, sign2,sign_greater,sign_smaller; //sign_greater, sign_smaller; reg [4:0] sig1, sig2;//significants of inputs -- 5 bits long reg [5:0]...
  14. P

    16 bits full adder implementation

    first design four bit adder from one bit adder .then you can design 16bit adder from 4 full adder circuit.the code is available for this module in Xilinx website.
  15. P

    WIPRO VLSI placements

    the important topics are the setup time and hold time violation ,tweaks for fixing this violation.and cover all front end steps(i.g. synthesis,verification ,STA)
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