preetam_24
Newbie level 6
I have performed synthesis of my RTL coding , after synthesis I performed formal verification there is no error. but when I am trying to do fullscan of synthesized code by DFT advisor(mentor graphics) it is not detecting whole flip flop. Out of 326 it is only convertring 294 F/F in to scannable F/F. So what may be the reason.
having full scan when I am checking for fault coverage by fastscan(mentor graphics) the result is not appropriate. I think by the virtue of this my fault coverage of whole design is 89% which is very less it should be more then 95%.
Note:- one thing is that after synthesis some of wire name changes so is that influencing my whole design?
please send me some appropriate solution.I will be grateful for that.
IT is very urgent please help me.
regards
preetam kumar
having full scan when I am checking for fault coverage by fastscan(mentor graphics) the result is not appropriate. I think by the virtue of this my fault coverage of whole design is 89% which is very less it should be more then 95%.
Note:- one thing is that after synthesis some of wire name changes so is that influencing my whole design?
please send me some appropriate solution.I will be grateful for that.
IT is very urgent please help me.
regards
preetam kumar
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