design compiler invoke for testability

[preetam_24]

currently i am working on synopsys design compiler.
I synthesized code very well after I have to move for scan insertion using synopsys TEST compiler. Is test compiler built in design compiler. could anybody tell me how to invoke/perform DFT(full scan+boundry scan) in design compiler because i tried necessary commands but it was unable to open DFT.just give me proper guidline. send me essential commands that is necessary for calling TEST Compiler in Design Compiler.

 

[tariq786]

Yadavvlsi can you take a look at this?

 

[preetam_24]

what is this yadavvlsi ans who is this wouldd u please clear to me

 

[shaival132]

I dont know if Synopsys DC has in-built TEST compiler or not, but yes if you want to do full-scan_boundasy scan you can use the tool DFT Compiler from Synopsys. Your first step should be to read in the systhesized netlist which you got rom DC as input to the DFT Compiler tool.

Few essential commands are

read_vhdl -netlist ./GCD_Cal.vhd

set_dft_signal -view existing_dft -type ScanClock -port clk -timing [list 45 55]
set_dft_signal -view existing_dft -type Reset -port rst -active_state 1

create_port -direction in SCAN_ENABLE
create_port -direction in SCAN_IN
create_port -direction out SCAN_OUT

set_dft_signal -view existing_dft -type ScanDataIn -port SCAN_IN
set_dft_signal -view existing_dft -type ScanDataOut -port SCAN_OUT
set_dft_signal -view existing_dft -type ScanEnable -port SCAN_ENABLE -active_state 1
set_dft_signal -view existing_dft -type ScanClock -port clk -timing [list 45 55]
set_dft_signal -view existing_dft -type Reset -port rst -active_state 1

# Insert the Scan Chain
insert_dft

write_file -format verilog -hierarchy -output ./GCD_Scan.v
write_file -format ddc -hierarchy -output ./GCD_Scan.ddc
write_test_protocol -output ./GCD_Scan.spf

 

[preetam_24]

thanky dear
it gave me some idea hopefully you will help me in future also.I will try definitely this method actually i have read yhis command somewhere else but but it was not clicked at that time


regards
preetam

---------- Post added at 08:17 ---------- Previous post was at 06:36 ----------

I am trying to do first step read_verilog -netlist/ netlist1.v but design compiler is giving file is not found. . I mean to say my synthesized verilog file is in /home/mtech05/ece128/netlist/netlist1.v . so should I follow this whole path read_verilog -/home/mtech05/ece128/netlist/netlist1.v .or directly write read_verilog -netlist/ netlist1.v. should I give this command after entering in to the design compiler or before.clearyfy to me.


regards
preetam

 

[preetam_24]

Error: Required argument 'file_names' was not found (CMD-007)
when I did from design compiler

 

[shaival132]

Error: Required argument 'file_names' was not found (CMD-007)
when I did from design compiler

You are supposed to read in the netlist in the DFT Compiler tool and all these commands to be executed in DFT Compiler. The output of the DC tool i.e. synthezized netlist acts as input to this DFT Compiler tool .