16 bits full adder implementation

[liusupeng]

HI, all
i want to make a 16 bits full adder circuits. I have read some paper and most of them talk how to minimize delay and power of a single bit fully adder cell. Should i cascade 16 1 bit full adder circuit to make my 16 bits full adder circuits? if so, the carry bit delay will be 16 times of the single bit cell and i believe it will be too much. is there any better way to implement it?

 

[preetam_24]

first design four bit adder from one bit adder .then you can design 16bit adder from 4 full adder circuit.the code is available for this module in Xilinx website.

 

[tariq786]

Please tell exactly what papers are you referring to?

Why do you have to cascade? You can make carry propagate adder, carry save adder, parallel prefix adder and so on.

 

[preetam_24]

module fxpt_adder(in1,in2,clk,result);
input clk;
input signed[32:0] in1,in2;
output signed [32:0] result;
parameter size = 33;

reg result_sign, sign1, sign2,sign_greater,sign_smaller; //sign_greater, sign_smaller;
reg [4:0] sig1, sig2;//significants of inputs -- 5 bits long
reg [5:0] result_sig;
reg [26:0] frac1, frac2;
reg [27:0] result_frac;
reg signed[32:0] result;
reg signed [32:0]in1_temp,in2_temp;

//assign in1_temp=in1;
//assign in2_temp=in2;
//assign in1_temp={sign1,sig1[4:0],frac1[26:0]};
//assign in2_temp={sign2,sig2[4:0],frac2[26:0]};
//assign result={result_sign,[5:1]result_sig,[27:1]result_frac};


always@(in1 or in2)begin

in1_temp=in1;
in2_temp=in2;
in1_temp={sign1,sig1[4:0],frac1[26:0]};
in2_temp={sign2,sig2[4:0],frac2[26:0]};

sign1 = in1[32]; //sign bit
sign2 = in2[32];

sig1 = in1[31:27]; //significand field
sig2 = in2[31:27];

frac1 = in1[26:0]; //fraction field
frac2 = in2[26:0];

sign_greater = (sig1 > sig2) ? sign1 : sign2;
sign_smaller = (sig1 > sig2) ? sign2 : sign1;

if(in1[32]==1)

in1_temp = {in1[32],!in1[31:0]+1};

else if (in2[32]==1)

in2_temp = {in2[32],!in2[31:0]+1};

end

always @(posedge clk)begin

if (in1 !=0 & in2!=0)

result_sign = sign_greater;
result_frac = frac1 + frac2;
result_sig = sig1 + sig2;

if(result_frac[27]==1)
result_sig = result_sig+1;

else if(result_sig[5]==1)begin

result_sig=result_sig[4:0];

result={sign_greater,result_sig[4:0],result_frac[27:1]};

end
end

endmodule
just try to undestand and make your code of 16bit

---------- Post added at 18:12 ---------- Previous post was at 18:02 ----------

here code is for 128 bit adder in verilog try and follow this definitely this will help you.

module adder_128bit (A, B, Sum);

input [127:0] A,B;
output [128:0] Sum;
wire [128:0] Sum;

wire [8:0] tempSum1, tempSum2, tempSum3, tempSum4, tempSum5, tempSum6, tempSum7, tempSum8;
wire [8:0] tempSum9, tempSum10, tempSum11, tempSum12, tempSum13, tempSum14, tempSum15, tempSum16;

wire tempCarry1, tempCarry2, tempCarry3, tempCarry4, tempCarry5, tempCarry6, tempCarry7, tempCarry8;
wire tempCarry9, tempCarry10, tempCarry11, tempCarry12, tempCarry13, tempCarry14, tempCarry15, tempCarry16;

wire f2, f3, f4, f5, f6, f7, f8;
wire f9, f10, f11, f12, f13, f14, f15, f16;

wire c1, c2, c3, c4, c5, c6, c7, c8;
wire c9, c10, c11, c12, c13, c14, c15, c16;

assign tempSum1 = A[7:0] + B[7:0];
assign tempSum2 = A[15:8] + B[15:8];
assign tempSum3 = A[23:16] + B[23:16];
assign tempSum4 = A[31:24] + B[31:24];
assign tempSum5 = A[39:32] + B[39:32];
assign tempSum6 = A[47:40] + B[47:40];
assign tempSum7 = A[55:48] + B[55:48];
assign tempSum8 = A[63:56] + B[63:56];
assign tempSum9 = A[71:64] + B[71:64];
assign tempSum10 = A[79:72] + B[79:72];
assign tempSum11 = A[87:80] + B[87:80];
assign tempSum12 = A[95:88] + B[95:88];
assign tempSum13 = A[103:96] + B[103:96];
assign tempSum14 = A[111:104] + B[111:104];
assign tempSum15 = A[119:112] + B[119:112];
assign tempSum16 = A[127:120] + B[127:120];

assign tempCarry1 = tempSum1[8];
assign tempCarry2 = tempSum2[8];
assign tempCarry3 = tempSum3[8];
assign tempCarry4 = tempSum4[8];
assign tempCarry5 = tempSum5[8];
assign tempCarry6 = tempSum6[8];
assign tempCarry7 = tempSum7[8];
assign tempCarry8 = tempSum8[8];
assign tempCarry9 = tempSum9[8];
assign tempCarry10 = tempSum10[8];
assign tempCarry11 = tempSum11[8];
assign tempCarry12 = tempSum12[8];
assign tempCarry13 = tempSum13[8];
assign tempCarry14 = tempSum14[8];
assign tempCarry15 = tempSum15[8];
assign tempCarry16 = tempSum16[8];

assign f2 = (tempSum2[7:0] == 8'hff);
assign f3 = (tempSum3[7:0] == 8'hff);
assign f4 = (tempSum4[7:0] == 8'hff);
assign f5 = (tempSum5[7:0] == 8'hff);
assign f6 = (tempSum6[7:0] == 8'hff);
assign f7 = (tempSum7[7:0] == 8'hff);
assign f8 = (tempSum8[7:0] == 8'hff);
assign f9 = (tempSum9[7:0] == 8'hff);
assign f10 = (tempSum10[7:0] == 8'hff);
assign f11 = (tempSum11[7:0] == 8'hff);
assign f12 = (tempSum12[7:0] == 8'hff);
assign f13 = (tempSum13[7:0] == 8'hff);
assign f14 = (tempSum14[7:0] == 8'hff);
assign f15 = (tempSum15[7:0] == 8'hff);
assign f16 = (tempSum16[7:0] == 8'hff);

assign c1 = tempCarry1;
assign c2 = (c1 & f2) | tempCarry2;
assign c3 = (c2 & f3) | tempCarry3;
assign c4 = (c3 & f4) | tempCarry4;
assign c5 = (c4 & f5) | tempCarry5;
assign c6 = (c5 & f6) | tempCarry6;
assign c7 = (c6 & f7) | tempCarry7;
assign c8 = (c7 & f8) | tempCarry8;
assign c9 = (c8 & f9) | tempCarry9;
assign c10 = (c9 & f10) | tempCarry10;
assign c11 = (c10 & f11) | tempCarry11;
assign c12 = (c11 & f12) | tempCarry12;
assign c13 = (c12 & f13) | tempCarry13;
assign c14 = (c13 & f14) | tempCarry14;
assign c15 = (c14 & f15) | tempCarry15;
assign c16 = (c15 & f16) | tempCarry16;

assign Sum[7:0] = tempSum1[7:0];

assign Sum[15:8] = c1 ? (tempSum2[7:0] + 1) : tempSum2[7:0];

assign Sum[23:16] = c2 ? (tempSum3[7:0] + 1) : tempSum3[7:0];

assign Sum[31:24] = c3 ? (tempSum4[7:0] + 1) : tempSum4[7:0];

assign Sum[39:32] = c4 ? (tempSum5[7:0] + 1) : tempSum5[7:0];

assign Sum[47:40] = c5 ? (tempSum6[7:0] + 1) : tempSum6[7:0];

assign Sum[55:48] = c6 ? (tempSum7[7:0] + 1) : tempSum7[7:0];

assign Sum[63:56] = c7 ? (tempSum8[7:0] + 1) : tempSum8[7:0];

assign Sum[71:64] = c8 ? (tempSum9[7:0] + 1) : tempSum9[7:0];

assign Sum[79:72] = c9 ? (tempSum10[7:0] + 1) : tempSum10[7:0];

assign Sum[87:80] = c10 ? (tempSum11[7:0] + 1) : tempSum11[7:0];

assign Sum[95:88] = c11 ? (tempSum12[7:0] + 1) : tempSum12[7:0];

assign Sum[103:96] = c12 ? (tempSum13[7:0] + 1) : tempSum13[7:0];

assign Sum[111:104] = c13 ? (tempSum14[7:0] + 1) : tempSum14[7:0];

assign Sum[119:112] = c14 ? (tempSum15[7:0] + 1) : tempSum15[7:0];

assign Sum[127:120] = c15 ? (tempSum16[7:0] + 1) : tempSum16[7:0];

assign Sum[128] = c16;

endmodule

 

[tariq786]

preetam could you tell what kind of adder this is?

I mean is it ripple carry or carry save or what?

Thanks

 

[preetam_24]

actually first is fixed point adder and second is simple 128 bit adder these are ripple carry adder.
i vave prob. could you tell me how to perform scan insertion in synipsys test compiler.

 

[tariq786]

Please post your question about scan insertion in Synopsys test compiler as i have never worked with that.

Thanks

 

[preetam_24]

i have synthesized code in Design compiler ,after that I have to perform testability could you give me essential commands for invoking Test compiler in synopsys.

---------- Post added at 19:36 ---------- Previous post was at 19:31 ----------

actually i was working on Mentor Graphics for scan insertion but I could'nt do .IN synopsys Design compiler performs whole operation from RTL-GDSII so I have to perform full scan and boundry scan but I dont know whether this test compiler is built in Dsign compiler or not.

 

[tariq786]

Hang on. Someone will do get to you.

Thanks

 

[preetam_24]

please ask your friend and help me

 

[liusupeng]

first design four bit adder from one bit adder .then you can design 16bit adder from 4 full adder circuit.the code is available for this module in Xilinx website.

Hi Preetam,
Thanks a lot for your reply! The 4 bit adder is a pure combinational circuit. It seems that the VHDL code make a sequential circuit of 16 bit adder which consists of the combinational 4 bit adder, registers and clocks. And the input to output delay should be 2 clock cycles if i am correct.
I want to know in practice does all 16 bit adders are sequencial circuits or the 16 bit adders can be pure combinational also.
The terms carry propagate adder, carry save adder, parallel prefix adder are referring to sequency circuit or combinational circuit?

 

[preetam_24]

actually all this component will be treated as sequential element during synthesis but output will be gate level netlist