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Recent content by optimuz

  1. O

    XMR in Verilog : Use models

    Hi , Can any one tell me what can be the use models of XMR's in verilog. Thanks.
  2. O

    Verilog testbench generator

    Hi, Anyone knows any software or scripts which can generate a verilog testbench for a Verilog design. I am not looking for a tbgen which uses dumb files. But a testbench to do a RTL Vs Netlist simulation. Where it can generate all input patters or combinations of corner cases and does a RTL -...
  3. O

    ROM using File IO in VHDL

    Can u pls give a more precise answer with a sample code. ---------- Post added at 13:03 ---------- Previous post was at 12:06 ---------- Without file IO , i did is like this. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity single_port is port ( clk : in...
  4. O

    ROM using File IO in VHDL

    Hi everyone, I am very new to VHDL. Can anyone help me here, to model a ROM using File IO . Thankyou
  5. O

    TCL scripting- Extraction of a segment from a text

    Hi, I am a begginer in tcl. I am trying with strings and arrays now. Can anyone tell me how can I extract a particular section of a line using tcl. For example let my line be @N: CG364 :"D:\Designs\Source\srl1.v":1:7:1:10|Synthesizing module srl1 I need to copy from ' | ' to the end. How it...
  6. O

    Absolute beginner in ASIC, FPGA and Computer architecture

    If you are planning to study Verilog HDL, I recommend you to study Samir Palnithkar. Digital design can alone be get mastered through Mori s Manno. For ASIC and FPGA flow , internet is best source. Search in Google leads you to get pictorial representation of Flows. And about architecture , as...
  7. O

    Mixing of Blocking and Non blocking assignments.

    @sharif.shiek Thanks for ur detail reply. For simulation purpose it is working fine. I have done with Xilinx ISE. But Synplify Pro which I am using for synthesizing is giving me error. My doubt is why it is giving error for ONLY second code , even though I am assigning constants .
  8. O

    Mixing of Blocking and Non blocking assignments.

    But my question is why tool is not taking a precidence like what it does for two variables. Anyway as its non blocking and blocking , it wont be assigning at the same time.
  9. O

    Mixing of Blocking and Non blocking assignments.

    Hi, I am having a problem when I am mixing Blocking and Non Blocking assignments . In the below code the tool is not giving any errors. always @ (*) begin x=1; z<=0; end But for this one , tool is giving error saying "cant mix blocking and non blocking" always @ (*)...
  10. O

    non blocking assignment in verilog

    Yes ofcourse I agree with u FvM. Thanks for finding it out for me.
  11. O

    non blocking assignment in verilog

    I hope the in NBA it needs three trigerring for the sensitivity list to get the same output as the blocking. Or else for better simulation view, that * can be replaced by a "posedge clk".
  12. O

    non blocking assignment in verilog

    Adding some more points to what cks3976 said. 1.About REG and WIRE. Both are verilog data types. If you want to assign or force some values to a particular variable inside your verilog code, you should use it as REG data type. Because REG has the capability of storing the value, but WIRE dint...
  13. O

    What do DV engineer do?

    Verilog, Sytem Verilog, OVM, UVM.
  14. O

    Behavioural and Functional simulation

    Can anyone explain me what exactly the difference between behavioural and functional simulation. I want to know why functional simulation after Synthesis. Thanks
  15. O

    [SOLVED] Xilinx ISE crashes while Running Tasks

    Found the reason myself :lol: always my_task (a,b,and_out,or_out); should be replaced with always @ * my_task (a,b,and_out,or_out);
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