ROM using File IO in VHDL

[optimuz]

Hi everyone,
I am very new to VHDL. Can anyone help me here, to model a ROM using File IO .

Thankyou

 

[optimuz]

Can u pls give a more precise answer with a sample code.

---------- Post added at 13:03 ---------- Previous post was at 12:06 ----------

Without file IO , i did is like this.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port is
port (
clk : in std_logic;
addr : in std_logic_vector (3 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end single_port;

architecture behav of single_port is

type rom_type is array (0 to 15) of std_logic_vector (7 downto 0);

constant content_rom : rom_type := (

0 => "01000001",
1 => "00000010",
2 => "00000011",
3 => "00110100",
4 => "00000101",
5 => "00110110",
6 => "00000111",
7 => "01111000",
8 => "00001101",
9 => "01101010",
10 => "11001011",
others => "11110010"
);

begin
p1: process(addr,clk)
begin
if (rising_edge(clk)) then
data_out<=content_rom(to_integer(unsigned(addr)));
end if;
end process p1;
end behav;

I need this data to be read from a file.