[SOLVED] Xilinx ISE crashes while Running Tasks

[optimuz]

Hi, My Xilinx ISE is getting crash when I tried a code for testing Task in Verilog.


What can be the probable reason for that. Even my machine which has 6gb ram with Xeon processor getting stuck and I need to restart the entire system.

Pls help,
Thanks in Advance

Attaching the code below this.

module tsk_tb;

//internal wires
reg [3:0]a,b;
wire and_out,or_out;

//instantiaition

tsk uut (.a(a),.b(a),.and_out(and_out),.or_out(or_out));

//initializing inputs

initial
begin
a=4'b1010;
b=4'b0000;
end

endmodule

module tsk (
input [3:0]a,b,
output reg and_out,or_out
);

task my_task;
input [3:0] a,b;
output and_out,or_out;
begin
and_out=a&&b;
or_out=a||b;
end
endtask

always my_task (a,b,and_out,or_out);


endmodule

 

[optimuz]

Hi, My Xilinx ISE is getting crash when I tried a code for testing Task in Verilog.


What can be the probable reason for that. Even my machine which has 6gb ram with Xeon processor getting stuck and I need to restart the entire system.

Pls help,
Thanks in Advance

Attaching the code below this.

module tsk_tb;

//internal wires
reg [3:0]a,b;
wire and_out,or_out;

//instantiaition

tsk uut (.a(a),.b(a),.and_out(and_out),.or_out(or_out));

//initializing inputs

initial
begin
a=4'b1010;
b=4'b0000;
end

endmodule

module tsk (
input [3:0]a,b,
output reg and_out,or_out
);

task my_task;
input [3:0] a,b;
output and_out,or_out;
begin
and_out=a&&b;
or_out=a||b;
end
endtask

always my_task (a,b,and_out,or_out);


endmodule

Found the reason myself :lol:

always my_task (a,b,and_out,or_out); should be replaced with always @ * my_task (a,b,and_out,or_out);