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Recent content by nsingh95

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    design of edge detection circuit

    try searching testbench.in or asic-world.com
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    Question about Mixed verilog/vhdl simulation in NCsim

    Hi nasim, Just try to remember one thing. In testbench there may be modules of both vhdl and verilog. When your testbench is verilog then whille creating instance make all the instance in verilog even the vhdl file. Similarly for vhdl testbench. I think ur problem is solved. regards, Nishi.
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    Setup time of a flip flop

    Hi , The setup time of the flip flop is totally technology dependent. Thats is the reason it use to change from vendors to vendors. It depends on the size of the transistors.... ie 35nm , 65nm, 45 nm. Regards, Nishi
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    Is this usefull or not?

    You have done a good job.Just remember that you have to gain vlsi skills. Download modelsim simulator, start coding modules and simulate it. This will boost up your skills. All the best...
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    Signal multiplication/Division

    Hi, You can use counter to generate different frequency clock from a reference clock.
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    Bitstream format and how it is organized within the FPGA

    Hi, Please visit altera site. Down load stratix iv data sheet. In the data sheet it clearly shows how to gerate bitstream and load into FPGA.
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    AT91SAM9260 boot from SD Card?

    Hi dariush, Please provide few more inputs.
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    calculate no LUTs,FLIP-FLOPS

    Hi all, Can you please give a suitable solution to find out no of LUTs,FFs utilization for a given expressio such as : c[2:0] = A.B +A.(B+C); Thanks....
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    sdf annotation problem

    Hi Uma, Two things: 1st : I think your design is in VHDL.So, please check whether a component of the module is declared or not in the file. i.e. suppose your design has cachemem.vhd [/B]which has an instance of memory i.e. dpram : inst (a;;''''''''')..... So please check whether the...
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    ADM1024 , INA209 , code

    Hi, Can anyone please provide me with ADM1024 , INA 209 verilog / vhdl code.
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    Can you use both clock edges in an FPGA?

    Hi, U can use both the edges of clk but it shd nt go for any timingviolations ... I don't find any issue in above code...
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    Clock Generation logic

    Hi , In ur testbench file: 1. Selct the time scale to ns write the foolowing lines : always #5 clk = ~clk; This will generate a clock of 100 Mhz freq and 10 ns time with 50% duty cycle. regards, Nishi
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    Question in Verilog RTL

    Hi , need to remove the " # " and try giving delay using some temp registers...
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    Interview Questions- Help Required

    Hi, www.testbench.in will be gud for u....
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    ASIC VERIFICATION INTERVIEW

    Hi , Since ur are fresher ... read morris mano... also the intel guys would expect you to write some Assembly level language... So read thoroughly abt microcomtroller, processor ...8085,8086 and their applications...
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