Signal multiplication/Division

[rajukonduru]

Hi Frnds of Great Brains im new to this vlsi world i need one help from you

my specifications are as below

one signal is generating at 60hz rate wt 65Mhz as clock as reference from that i need to generate 120hz rate how do i proceed i will be very much thank ful if the code is presented in VHDL.


thanks in advance

 

[FvM]

This isn't a complete specification. You neither specify the characteristic of the 60 Hz "signal" nor the required relation of newly generated 120 Hz signal to the 60 Hz input. You could e.g. generate a 120 Hz signal by dividing 65 MHz without using the 60 Hz.

 

[bigdogguru]

Are you attempting to generate different clocks from a master clock? If so it sounds like you need to utilize a Xilinx DCM or Altera PLL. Check out:



If this is what your looking for, let me know the manufacturer and model of the FPGA your using, I may have some PDFs that describe their implementation.

Those are very low clock rates to generate from a 65MHz master, so additional logic will have to be employed.

Ciao

 

[rajukonduru]

Hello Sir, firstly im very thank ful for responding to my question, im sorry for not giving the complete info regarding the signal generation.

here are my specifications one signal is generating at 60hz that is ON period of that signal is 5 micro seconds and OFF period is 11 micro seconds, with a reference clk of 65Mhz which is derived from Altera PLL, taking the reference of that 60hz signal i need to generate 120hz signal with the same 65Mhz as reference clock. i need this in vhdl language.

thanks in advance

 

[FvM]

I have two problems with your post:
- The numbers don't fit. 5 + 11 usec on/off would result in 66.6 kHz rather than 60 Hz.
- I have difficulties to refer your signal description ("is generating... with a reference clock") to a hardware structure

Is the 60 Hz (or kHz?) signal generated by a frequency divider from the said 65 MHz? Or is it an unrelated signal? In the first case, you would simply extend the frequency divider to generate the second signal, too.

 

[rajukonduru]

here is the code for which i have written sir once u check out
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity vsync is
port (
clk : in std_logic;
vsync_out : out std_logic
);
end vsync;

architecture rtl of vsync is

signal rst : std_logic;
signal rst_cntr : std_logic_vector(7 downto 0):= x"00";

signal vsync_cntr : std_logic_vector(15 downto 0);
signal vsync_1 : std_logic;

signal vsyn_cntr1 : std_logic_vector(15 downto 0);
signal vsync_2 : std_logic;

signal lock : std_logic;

begin

process(clk)
begin
if rising_edge(clk) then
if rst_cntr = 15 then
rst <= '0';
else
rst <= '1';
rst_cntr <= rst_cntr + 1;
end if;
end if;
end process;

process(clk,rst)
begin
if rst = '1' then
vsync_cntr <= (others => '0');
vsync_1 <= '0';
elsif rising_edge(clk) then

if vsync_cntr = 1079 then
vsync_cntr <= (others => '0');
vsync_1 <= '1';
else
vsync_cntr <= vsync_cntr + 1;
end if;

if vsync_cntr = 325 then
vsync_1 <= '0';
end if;

end if;
end process;

end rtl;

clk is 65Mhz

hope ill get an ans for this from you sir

 

[nsingh95]

Hi,
You can use counter to generate different frequency clock from a reference clock.

 

[FvM]

To get another output of double frequency, you can simply derive the signal from the same counter. The frequency is not exactly 120 kHz, according to the divider ratio you selected. To get 60/120 kHz exactly, change the divider ratio respectively.

if vsync_cntr = 1079 OR  vsync_cntr = 539 then
  sync120 <= '1';
elsif vsync_cntr = 809 OR  vsync_cntr = 269 then
  sync120 <= '0';
end if;

 

[rajukonduru]

Thank you for your valuable ans sir one more question
im getting a signal whose on period is 10 microseconds and off period is 50 microseconds and another signal is inverted to it i mean off period is 10 microseconds and on period is 50 microseconds with the clock of 16.25Mhz, by comparing both the signals i need to generate a final signal either it may be the first case or the second case. with the same clock frequency..

 

[rajukonduru]

hi frnds
im having one doubt im using a two port dpram from altera megawizard where in my wrside data is 8bits wide and rd side i need 48bits but its not giving the desired data to me wt i need to do is there any solution plz let me know thnks in advance wt ever the AW may be

 

[FvM]

Dual port with different port width is generally supported by RAM MegaWizard.