Question in Verilog RTL

[srinivasansreedharan]

Hi,
I wrote the following RTL for my I2C project. Dynamic Simulation in Modelsim worked fine for sda_out. But after synthesis I found that sda_out was connected to 1'b1. Also after place and route , the data_in[0] was not connected to any nets.

How do I represent the same in another way?

case(x)
a :
begin
sda_out = data_in[0];
#30 sda_out = 1'b1;
sm = st10;
end

 

[rakko]

#30 doesn't mean anything to synopsys and is getting ignored. you are assigning two values to a single variable in one process so synopsys usese the last assignment and ties your varable high.
you need an enable it usually is called sda_oen. Ues this enable to know the direction of your data. This output enable is usually generated from scl. see I2c design on OPEN CORE site for more details.

 

[nsingh95]

Hi,
I wrote the following RTL for my I2C project. Dynamic Simulation in Modelsim worked fine for sda_out. But after synthesis I found that sda_out was connected to 1'b1. Also after place and route , the data_in[0] was not connected to any nets.

How do I represent the same in another way?

case(x)
a :
begin
sda_out = data_in[0];
#30 sda_out = 1'b1;
sm = st10;
end

Hi ,
need to remove the " # " and try giving delay using some temp registers...

 

[rca]

Yeh, the code, you have wrote, is not a synthesizable code, you should have some warning when the line with # has been read.