Can you use both clock edges in an FPGA?

[uoficowboy]

Hi - I have a vague memory from when I did some FPGA work years and years ago that you cannot use both edges of a clock. In other words, something like:

process (Clk) begin
if (Clk'Event and Clk = '1') then
A <= '1';
elsif (Clk'Event and Clk = '0') then
A <= '0';
end if;
end process;

It seems like perfectly valid VHDL, but is there something inherent in an FPGA that doesn't allow this for some reason? Or is my memory wrong and it is perfectly fine to do this?

Thanks!

 

[cah1]

The devices I'm familiar with have flip-flops with programmable clock polarities but are fixed - either rising or falling. There are input DDR registers in devices like Xilinx Virtex but I doubt if this is what you have in mind. I don't know what this code would synthesize into.

 

[supercat]

Hi - I have a vague memory from when I did some FPGA work years and years ago that you cannot use both edges of a clock.

Some logic devices include options to have clocks which latch data on both edges of the clock. Others do not include such logic.

In theory, one could simulate such a device by using two level-sensitive latches, which operate on opposite clock edges, and a multiplexer which uses the clock input to select between them. If a hazard-free multiplexer is used, this will work nicely provided the data input doesn't change any time near clock transitions. If a clock and data transition could occur in close proximity, however, there are many scenarios where simultaneous edges on clock and data could cause the output to switch twice in rapid succession. There are cases where runt pulses wouldn't be a problem, and there other ways of coding logic to avoid them, but they all involve trade-offs. Generally, if one needs double-edge logic, one has to provide for it oneself.

 

[shitansh]

for this perhaps combinatorial design is proffered.

HTH

 

[yanzixuan]

A d flip-flop only has one clock driver. So a d-ff can not be triggered both rising and falling.
DDR uses 2 D-ff: one is triggered rising , and the other is triggered falling.

 

[lucbra]

This is typical the software approach error.

Pls refer to the datasheet of any FPGA. You will notice that none has flip-flops that can clock on both edges. Even the DDR registers split the rising and falling edge in two FF's.

I recommend to anyone that I teach VHDL (for FPGA or PLD) to start thinking hardware.

If you compile the design with this code, you will certainly get an error.

Regards,
L

 

[nsingh95]

Hi - I have a vague memory from when I did some FPGA work years and years ago that you cannot use both edges of a clock. In other words, something like:

process (Clk) begin
if (Clk'Event and Clk = '1') then
A <= '1';
elsif (Clk'Event and Clk = '0') then
A <= '0';
end if;
end process;

It seems like perfectly valid VHDL, but is there something inherent in an FPGA that doesn't allow this for some reason? Or is my memory wrong and it is perfectly fine to do this?

Thanks!

Hi,
U can use both the edges of clk but it shd nt go for any timingviolations ...
I don't find any issue in above code...

 

[rca]

there is not issue to write/simulate this code, but there is not physical way to implement it, no standard cell exist.

 

[goshka]

You can use posedge clk2.
(freq(clk2)= 2*frq(clk)

 

[supercat]

Would the approach in be a good one (uses two AR/AP flip-flops, but both should settle on right value after each edge).

 

[mpatel]

Hi,
The code written above can not be synthesized. But there is a solution. You need to use two different processes, one at positive edge and other at negative edge. After your processes finish you need to write a logic to select your signals and transfer the value to the output.

Please read this book. It gives really good idea about dual edge flip flop and other FPGA hardware related issues.

Advanced FPGA Design : Architecture, Implementation and Optimization by Steve KILTS

Have a nice time!
Mukesh

 

[permute]

indeed, this will be fpga dependent. Keep in mind that FPGAs might offer special IDDR/ODDR elements for the IO.

otherwise you have to implement the logic in two processes. Also pay special attention if the logic is crossing a clock boundary, as skew may be an issue.

 

[FvM]

You can have actions for both clock edges in one process, but not for the same signal.

 

[ranjana.foru]

using both edges to synthesize same signal is nt possible and even with sum compilers it will nt give any error but still its nt recommended ,a bad programming style .
but yes using two process for two events n for two different signals is fine

 

[JasonHil]

I want live of my own. Because normal i am alone.