Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
class ab amplifier schematic
the schematic posted here is a typical class A amplifier. As we see there is a passive element for pull up. The distortion mentioned in the class AB amplifier is due to the transition between pull up and pull down devices (active). this distortion can be minimized...
class ab biasing
practically class AB amplifiers can be divided in to two stage
gain stage and driver stage. In the driver stage push & pull section controlled based on the voltage at the gain stage. ( this may be your interpretation of change in the bias)
But this change is due to the...
after visual inpection of the circuit,
your startup circuit looks me as three stage maplifier, with multiple dominant poles, can you check the circuit with different statup scheems ?
hi
the output impedance of the second amplifier(R) will reduce because of the negetive feed back (through the miller capacitor)
thats why the output pole moves away from the origine
hope i answered your question
:D
\]
unity-gain bandwidth
I believe you know that,
prodct of gain and bandwidth remain constant, this wil answer your question.
As frequency increases for a given load, amplifier is not capable to change the voltage in a given duration of time, hence swing decreses, this will reduce the gain...
bandwidth on a comparator
In simple words, it dependds on ur system requirements.
In case u need to just identify the incoming pulse, its delay should be less than the next pulse appear at the input.
As i know for comparators we generaly talk about delay rather than bandwidth
regards
1) your differential signal is out of comman mode range, as you connected the both other teminal to ground.
so tail current source no longer tail current source(get in to linear region)
2) in case i am wrong , you can achive good bandwidth by cascading low gain amplifier
you can achive this by...
Hi
The counter question is how much delay you want to achive
you should stop the invertor chain when it rise/fall time is comparable to the delay of the inverot chain(say equal, or half )
This may take few nano seconds, based on your technology
Added after 3 minutes:
one more thing i...
Re: Constant Gm biasing
behzad razavi has good info on this
constant gm biasing also uesd in opamps having rail to rail comman mode range,
there we boost the bias current of n diff pair or pdiff pair, when the input comman mode voltage come near to rail to meet the gain constant
Re: Charge Sharing
If you have a capacitor charged to a voltage v1
then you connect another capacitor in parellel, which is charged to a voltage v2
then some charge from the capacitor charged to high voltage go to other capacitor
and now , voltage across both those capacitor is v3, which is...
No simple solution
1)If you want to use precise 1.8 and .6V need to go for bandgap and then generate other buffered voltage which you can use as supply and ground for a simple invertor(to get the required swing)
2) if you dont whant exact voltage(1.8V, .6V) you can exploit the vt of the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.