Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help: the delay of inverter driver !

Status
Not open for further replies.

gdhp

Advanced Member level 4
Joined
Jan 7, 2005
Messages
116
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,298
Activity points
931
HI ALL
I am designing a inverter driver to drive a 20-50pf capcitance. i use the

cascade of inverter structure (each is two times than the last one). But the delay

is too large to damage the timing.

So is there other method to do this things?

thanks!

Added after 1 hours 16 minutes:

no reply??
 

Hi
The counter question is how much delay you want to achive
you should stop the invertor chain when it rise/fall time is comparable to the delay of the inverot chain(say equal, or half )
This may take few nano seconds, based on your technology

Added after 3 minutes:

one more thing i forgot to mention
in case you have a very long invertor chain, dont allow first few stage to saturate, this will buy you some time ,
this is conventional high speed io design strategy
regards
 

can you get more details,
what voltage, current you are planning to get of it?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top