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Recent content by muthuram1984

  1. M

    Binary to gray conversion in FIFO pointer

    Hi, We are using gray code value in Read and write pointers in FIFO to avoid the multi bit changing in single clock cycle,for example if you are using the async FIFO with the depth of 11 and width of 32bits. So now the write pointer will be reset to zero when it reaches the 10th location so...
  2. M

    Timing optimisation technique(Pipelining)

    Thanks shaiko and pavanks for your reply..it is helpful :)
  3. M

    Timing optimisation technique(Pipelining)

    Hi, One of the timing optimisation technique in ASIC design is pipelining, i would like to know about this technique in detail please could you explain any one of you about this technique? Here is the example 10bit full adder is there it is working in 10Mhz,so i want to make this adder...
  4. M

    [MOVED]FIFO Depth calculation For same frequency

    Re: FIFO Depth calculation For same frequency Thanks Vijay It is useful :)
  5. M

    [MOVED]FIFO Depth calculation For same frequency

    Hi, Please let me know how we can calculate the FIFO Depth if the source and Destination frequncies are same but both are asynchronous(may be phase Difference)? Thanks
  6. M

    sequence detector using FSM technique

    Hi, I have to design a sequence detectors for the serial inputs for the following conditions using FSM 1. It should give output as one when it detects the sequence "1010" 2. It should give output as one when it detects the sequence which is divisable by 5(eg. 1010, 0101) Please let me know...
  7. M

    Timing analysis and delay path

    Shall we say like this " A timing path which take more number of specified hierarchies in design" Do you have any example for this? Thanks Muthu
  8. M

    Clock domain crossing

    You mean i have to extend the pulse for 5 clock cycle like for example the pulse signal called as "test" then you have to generate test_d , test_2d,test_3d test_4d then the resultant pulse should be res_test = test | test_d | test_2d | test_3d | test_4d; So this resultant pulse should be...
  9. M

    Timing analysis and delay path

    What is meant by "Snake Path"?
  10. M

    Clock domain crossing

    Hi, Please i need a synchronistion technique for the below CDC 1. Source clock 400Mhz 2. Destination clock 80 Mhz A pulse is generated in 400Mhz clock domain and between two pulses there is only two clock cycle difference is there So how can we synchronise this pulses into the 80Mhz clock...
  11. M

    FIFO full and Empty flags

    I need the explantions for the follwoing terms 1.Almost full and empty flags 2.Pessimistic full and empty flags Thanks Muthu
  12. M

    Memory verification using testbench.

    I am using Verilog HDL.But my doubt is how can we bring up this memory read problem using verilog test bench? We can randomise the Address,payload data by using random constructs aparat from that how can we bring up this issue using our test bench? Thanks Muthu
  13. M

    Clock distribution and network

    Hi all, Please explain the term "Clock Race" Thanks Muthu
  14. M

    Memory verification using testbench.

    Hi all, Please explain how we can verify a Memory using testbench?..For example i am writing data to a location 10 and reading from that location.but it is giving the data from the location 20...... so how can i verify that? Thanks ASICan
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