Clock domain crossing

[muthuram1984]

Hi,

Please i need a synchronistion technique for the below CDC

1. Source clock 400Mhz
2. Destination clock 80 Mhz

A pulse is generated in 400Mhz clock domain and between two pulses there is only two clock cycle difference is there
So how can we synchronise this pulses into the 80Mhz clock domain? I think handshaking wont work for this it will miss the pulse.

Source clock 5clock cycle = 1 destination clock cycle. Please explain in detail.

Thanks
Muthu

 

[barry]

Are the two domains synchronous? If they are in an FPGA (or ASIC) you can add constraints in your tools.

One way is to make your pulse 5 400MHz clocks wide, and then use a 2-FF synchronizer in your 80MHz domain.

 

[muthuram1984]

You mean i have to extend the pulse for 5 clock cycle like

for example the pulse signal called as "test" then you have to generate test_d , test_2d,test_3d test_4d then the resultant pulse should be

res_test = test | test_d | test_2d | test_3d | test_4d;

So this resultant pulse should be given to destination clock after double flopping that...Am i right here?.
But here clock latency will take more isnt it?...is it ok? or we have to move some other technique?

 

[barry]

I would generate the pulse differently (using a counter, e.g.). But the point is you need to have a pulse at least as wide as the period of the slow clock, otherwise, the chances of a 2.5nS wide pulse occuring at the same time as your 80MHz clock edge are small.

You should investigate twol-register synchronizers; there is lots of information on the web that will do a better explanation than I would here. But the wide pulse if given to two flops that are clocked by the slow clock, not the fast one.