Timing optimisation technique(Pipelining)

[muthuram1984]

Hi,

One of the timing optimisation technique in ASIC design is pipelining, i would like to know about this technique in detail
please could you explain any one of you about this technique?

Here is the example

10bit full adder is there it is working in 10Mhz,so i want to make this adder work for 20Mhz,so how will you apply pipelining technique for this adder circuit to make it work for 20Mhz?

I will appreciate if you able to explain using this example.

Thanks
Muthu

 

[shaiko]

Read this:
https://vhdlguru.blogspot.com/2011/01/what-is-pipelining-explanation-with.html

In principle, pipelining is a technique to tradeoff latency for speed.

 

[pavanks]

So as the frequency now is double and ur clock period will become half now.
Now by adding a register between a timing path u can reduce the Arrival time so that it meets the new clock period.

This is the logic behind the pipelining. U can find lot of materials here in edaboard pls search it in ASIC methadologies and tools.
But here there is a big disadvantage of inc in area and power.

 

[muthuram1984]

Thanks shaiko and pavanks for your reply..it is helpful