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Static Timing analysis

This is the third time this week someone asks about STA flow. I have never seen anyone call anything STA flow in the past decade. I assume you mean logic synthesis... if so, yes, you can do it without lef. there is no good reason for it though. if you have the LEF files, just use them.
 
STA is one of the feedbacks for synthesis.

The design flow should be telling you what you need and
what you need to do, not us. We don't know your tools
(lef and def pertain, I believe, to Synopsys compiler?).


Are we just a substitute for reading documents that you
were supposed to, but are too lazy? Should we maybe


to make your life easier?
 
This is the third time this week someone asks about STA flow. I have never seen anyone call anything STA flow in the past decade. I assume you mean logic synthesis... if so, yes, you can do it without lef. there is no good reason for it though. if you have the LEF files, just use them.
okay thank you for your response

but my confusion is whether LEF file is compulsory for STA Analysis after PostRoute Stage or not?
 
ok, that is a very different question.

you can't reach post route stage without LEF. LEF determines pin locations of the cells. without LEF, there is no routing.

but I stand by my previous comment. if you have LEF files, just use them. this is the industry flow for as long as I can remember. what is the motivation for not using it? I don't get it.
 

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